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datasheet r01ds0257ej0200 rev.2.00 page 1 of 133 apr 14, 2017 rx24t group renesas mcus features 32-bit rxv2 cpu core ? max. operating frequency: 80 mhz capable of 153.6 dmips in operation at 80 mhz ? enhanced dsp: 32-bit multi ply-accumulate and 16-bit multiply-subtract in structions supported ? built-in fpu: 32-bi t single-precisio n floating point (compliant to ieee754) ? divider (fastest instruction ex ecution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architectur e with 5-stage pipeline ? variable-length instruct ions, ultra-compact code ? on-chip debugging circuit ? memory protection unit (mpu) supported low power design and architecture ? operation from a single 2.7-v to 5.5-v supply ? three low power c onsumption modes on-chip code flash memory ? 512-/384-/256-/128- kbyte ca pacities ? on-board or off-board user programming ? for instructions and operands on-chip data flash memory ? 8-kbyte (number of erase/write cycle s: 1,000,000 (typ)) ? bgo (back ground operation) on-chip sram, no wait states ? 32-/16-kbytes of sram data transfer functions ? dtc: four transfer modes reset and supply management ? seven types of reset , including the power-on reset (por) ? low voltage detection (l vd) with voltage settings clock functions ? main clock oscillator frequency: 1 to 20 mhz ? external clock input frequency: up to 20 mhz ? pll circuit input: 4 mhz to 12.5 mhz ? on-chip low-speed oscillato rs, on-chip high-speed oscillators, dedicated on-chip oscillator for the iwdt ? clock frequency accuracy m easurement circuit (cac) independent watchdog timer ? 15-khz on-chip oscillator produces a dedicated clock signal to drive iwdt operation. useful functions for iec60730 compliance ? self-diagnostic and disconnection-dete ction assistance functions for the a/d converter , clock frequency accuracy measurement circuit, independent watchdog timer, ram test assistance functi ons using the doc, etc. mpc ? multiple locations are selectable for i/o pins of peripheral functions up to 6 communications channels ? can (compliant with is o11898-1), incorporating 16 message boxes (1 channel) ? sci with many useful functions (3 channels) asynchronous mode, clock sync hronous mode, smart card interface mode, simplified spi, simplified i 2 c, and extended serial mode. ? i 2 c bus interface: transfer at up to 400 kbps, capable of smbus operation (1 channel) ? rspi capable of high speed connection transfer at up to 20 mbps (1 channel) up to 25 extended-function timers ? 16-bit mtu3: 80 mhz operati on, input capture, output compare, three-pha se complementary p wm 2 channels output, cpu-efficient comp lementary pwm, phase counting mode ( nine channels) ? 16-bit gpt: 80 mhz operatio n, input capture, output compare, pwm wave-form single-phase complementary 4 channels output o r three-phase 1 channel + single- phase complementary 1 channel output, comparator interlocking operation (count operation, pwm negate control) (4 channels) ? 8-bit tmrs (8 channels) ? 16-bit compare-match timers (4 channels) 12-bit a/d converter: 22 channels in 3 units ? incorporating sample-and-hold circuit 12 bits 3 units (unit 0: 5 channels, unit 1: 5 channels, unit 2: 12 channels) ? sampling time can be set for each channel ? group scan priority cont rol mode (3 levels) ? self-diagnostic func tion and analog input disconnection detection assistance func tion (compliant to iec60730) ? input signal amplitude by the programmable gain amplifier (4 channels) ? adc: 3-channel simultaneous s ample-and-hold circuit (3 shunt method), double data r egister (1 shunt method), amplifier (4 channels), comparator (4 channels) 8-bit d/a converter: 2 channels ? this can be used as referenc e voltage for a comparator register write protection function can protect values in important registers against overwriting. up to 81 pins for general i/o ports ? 5-v tolerant, open drain, input pull-up, switching of driving capacity operating temperature range ? C40 to +85c applications ? general industrial a nd consumer equipment plqp0100kb-b 14 x 14 mm, 0.5 mm pitch plqp0080ja-a 14 x 14 mm, 0.65 mm pitch plqp0080kb-b 12 x 12 mm, 0.5 mm pitch plqp0064kb-c 10 x 10 mm, 0.5 mm pitch r01ds0257ej0200 rev.2.00 apr 14, 2017 80-mhz 32-bit rx mcus, on-chip fpu, 153.6 d mips, power supply 5 v, 12-bit adc (equipped with 3-chann el synchronous s/h circuits, d ouble data registers, operating amplifiers, comparator) 3 units, simultaneous sampling up to adc 5 channels , can, 80-mhz pwm (three-phase complem entary output 2 channels + sin gle-phase complementary output 4 channels or three-phase complem entary 3 channels + single-ph ase complementary 1 channel)
r01ds0257ej0200 rev.2.00 page 2 of 133 apr 14, 2017 rx24t group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications, and table 1.2 gives a comparison of the functi ons of the products in differe nt packages. table 1.1 shows the outline of maximum sp ecifications, and the numbers o f peripheral modules and of channels of the modules differ depending on chip version and the pin number on the package. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/4) classification module/function description cpu cpu ? maximum operating frequency: 80 mhz ? 32-bit rx cpu (rx v2) ? minimum instruction execution time: one instruction per clock c ycle ? address space: 4-gbyte linear ? register set general purpose: sixteen 32-bit registers control: ten 32-bit registers accumulator: two 72-bit registers ? basic instructions: 75 variable-length instruction format ? floating-point instructions: 11 ? dsp instructions: 23 ? addressing modes: 11 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32-bit 32-bit 64-bit ? on-chip divider: 32-bit 32-bit 32-bit ? barrel shifter: 32 bits ? rom cache: 2 kbytes (disabled by default) fpu ? single precision (32-bit) floating point ? data types and floating-point exc eptions in conformance with the ieee754 standard memory rom ? capacity: 128 k/256 k/384 k/512 kbytes ? up to 32 mhz, no-wait memory access 32 to 80 mhz: wait states ? off-board programming ? programming/erasing method: serial programming (asynchronou s serial communication), self-pr ogramming ram ? capacity: 16 k/32 kbytes ? 80 mhz, no-wait memory access e2 dataflash ? capacity: 8 kbytes ? number of erase/write cycles: 1,000,000 (typ) mcu operating mode single-chip mode clock clock generation circuit ? main clock oscillator, low- and high-speed on-chip oscillators, pll frequency synthesizer, and iwdt- dedicated on-chip oscillator ? independent settings for the system clock (iclk), peripheral mo dule clock (pclk), and flashif clock (fclk) the cpu and system sections such a s other bus masters run in sy nchronization with the system clock (iclk): 80 mhz (at max.) the mtu3 and gpt modules run in synchronization with the pclka: 80 mhz (at max.) the peripheral modules other than mtu3 and gpt run in synchronization with the pclkb: 40 mhz (at max.) adclk operated in s12ad runs in synchronization with the pclkd: 40 mhz (at max.) the flash memory peripheral cir cuit runs in synchronization wit h the fclk: 32 mhz (at max.) resets res# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset voltage detection voltage detection circuit (lvdab) ? when the voltage on vcc falls below the voltage detection level , an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detecti on voltage from 3 levels voltage detection circuit 1 is capable of selecting the detecti on voltage from 9 levels voltage detection circuit 2 is capable of selecting the detecti on voltage from 4 levels low power consumption low power consumption functions ? modu le stop function ? three low power consumption modes sleep mode, deep sleep mode, and software standby mode function for lower operating power consumption ? operating power control modes high-speed operating mode and middle-speed operating mode
r01ds0257ej0200 rev.2.00 page 3 of 133 apr 14, 2017 rx24t group 1. overview interrupt interrupt controller (icub) ? interrupt vectors: 163 ? external interrupts: 9 (nmi, irq0 to irq7 pins) ? non-maskable interrupts: 5 (nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority dma data transfer controller (dtca) ? transfer modes: normal transfer, repeat transfer, and block tra nsfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 100-pin/80-pin/64-pin ? i/o: 80/60/48 ? input: 1/1/1 ? pull-up resistors: 80/60/48 ? open-drain outputs: 60/45/37 ? 5-v tolerance: 2/2/2 multi-function pin controller (mpc) capable of selecting the inp ut/output function from multiple pins timers multi-function timer pulse unit 3 (mtu3d) ? 9 units (16 bits 9 channels) ? provides up to 28 pulse-input/output lines and three pulse-inpu t lines ? select from among fourteen counter-input clock signals for each channel (pclk/1, pclk/2, pclk/4, pclk/8, pclk/16, pclk/32, pclk/64, pclk/256, pclk/1024, mtclka, mtclkb, mtclkc, mtclkd, mtioc1a) other than channel 1/3/4/6/7, for which only e leven signals are available, channel 2 for 12, channel 5 for 10 ? 43 general registers including 28 output compare/input capture registers ? counter clear operation (with compare match- or input capture-s ourced simultaneous counter clear capability) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous register input/output by synchronous counter opera tion ? buffer operation ? cascaded operation ? 45 interrupt sources ? automatic transfer of register data ? pulse output modes: toggle/pwm/complementary pwm/reset-synchronized pwm ? complementary pwm output mode 3-phase non-overlapping waveform output for inverter control automatic dead time setting adjustable pwm duty cycle: from 0 to 100% a/d conversion request delaying function interrupt at crest/trough can be skipped double buffer function ? reset-synchronized pwm mode outputs three phases each for positive and negative pwm wavefor ms in user-specified duty cycle ? phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2) ? dead time compensation counter function ? a/d converter start trigger can be generated ? a/d converter start triggers can be skipped ? signals from the input capture and external counter clock pins are input via a digital filter port output enable 3 (poe3b, poe3a) ? poe3b control of the high-impedance state of the mtu3's waveform outp ut pins startup by input from signal sources on 6 pins (poe0#, poe4#, p oe8#, poe10#, poe11#, and poe12#) startup by detection of short-ci rcuited outputs (detection of s imultaneous pmw output at the active level) st artup by detection of oscillation stopping or by a comparator , or under software control control of addition of pins for output control is programmable ? poe3a (the following functions are added to the poe3b) control of the high-impedance state of gpt's waveform output pi ns control of the mtu3/gpt waveform output pins and switching them to operate as general i/o ports a comparator detection interrupt source can be set for each out put pin group table 1.1 outline of specifications (2/4) classification module/function description
r01ds0257ej0200 rev.2.00 page 4 of 133 apr 14, 2017 rx24t group 1. overview timers general pwm timer (gptb) ? 16 bits 4 channels ? two channels can be cascaded and used as a 32-bit timer ? counting up or down (saw waves), or counting up and down (trian gle waves) is selectable for each counter. ? a count clock is selectable from 13 types (pclk/1, pclk/2, pclk /4, pclk/8, pclk/16,pclk/32, pclk/64, pclk/256, pclk/1024, gteclka, gteclkb, gteclkc, and gt eclkd) for each channel. ? two i/o pins per channel ? two output compare/input capture registers per channel ? for the two output compare/input capture registers of each chan nel, 4 registers are provided as buffer registers and are capable of operating as comparison reg isters when buffering is not in use. ? in output compare operation, buffer switching can be at crests or troughs, enabling the generation of laterally asymmetric pwm waveforms. ? registers for setting up frame cycles in each channel (with capability for generating interrupts at overflow or underflow) ? synchronous operation of the several counters ? modes of synchronous operation (s ynchronized or displaced by a desired time to obtain relative phase shifts) ? generation of dead times in pwm operation ? through combination of three counters, generation of three-phas ed pwm waveforms incorporating dead times ? starting, clearing, and stopping counters in response to extern al or internal triggers ? internal trigger sources: output of the comparator detection, m tu3 count start, software, compare match ? noise filter function for signals on the input capture, externa l trigger pins, and the external count clock pins ? a/d converter start triggers can be generated compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four clock signals (pclk/8, pclk/32, pclk/128 , pclk/512) independent watchdog timer (iwdta) ? 14 bits 1 channel ? count clock: dedicated low-speed on-chip oscillator for the iwd t-dedicated on-chip oscillator frequency divided by 1, 16, 32, 64, 128, or 256 8-bit timer (tmr) ? (8 bits 2 channels) 4 units ? seven internal clocks (pclk/1, p clk/2, pclk/8, pclk/32, pclk/64 , pclk/1024, and pclk/8192) and an external clock can be selected ? pulse output and pwm output with any duty cycle are available ? two channels can be cascaded and used as a 16-bit timer ? generates a/d conversion start trigger ? generates baud rate clock for the sci5 and sci6 communication functions serial communications interfaces (scig) ? 3 channels (channel 1, 5, and 6: scig) ? scig serial communications: asynchr onous, clock synchronous, and smart-card interface on-chip baud rate generator allows sele ction of the desired bit rate selection of lsb-first or msb first transfer average transfer rate clocks for sci5 and sci6 can be input fro m tmr timers simple i 2 c simple spi multi-processor function detection of the start bit: level or edge is selectable. 9-bit transfer mode bit rate modulation i 2 c bus interface (riica) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master mode or slave mode selectable ? supports fast mode can module (rscan) ? single channel ? iso11898-1 specifications compliant (standard and extended fram es) ? 16 message boxes serial peripheral interface (rspib) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) signals enables serial transfer through spi operat ion (four lines) or clock-synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or received in a single tr ansfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception table 1.1 outline of specifications (3/4) classification module/function description
r01ds0257ej0200 rev.2.00 page 5 of 133 apr 14, 2017 rx24t group 1. overview 12-bit a/d converter (s12adf) ? 12 bits (5 channels 2 units/12 channels 1 unit) ? 12-bit resolution ? minimum conversion time: 1.0 s per channel when the adclk is o perating at 40 mhz ? operating modes scan mode (single scan mode, continuous scan mode, and 3 group scan mode) group a priority control (only for 3 group scan mode) ? sampling variable sampling time can be set up for each channel ? self-diagnostic function ? double trigger mode (a/d conversion data duplicated) ? assist on analog input disconnection detection ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu3, gpt, tmr), or an external trigger signal ? sample-and-hold function sample-and-hold circuit included (3 channels for unit 1) ? amplification of input signals by a programmable gain amplifier (1 channel for unit 0, 3 channels for unit 1) amplification rate: 2.0 times, 2.5 times, 3.077 times, 3.636 ti mes, 4.0 times, 4.444 times (total of 6 steps) comparator c (cmpc) ? 4 channels ? function to compare the reference voltage and the analog input voltage ? reference voltage: select from among two voltages ? analog input voltage is selectable from 4 inputs 8-bit d/a converter (da, daa) ? da 1 channel 8-bit resolution output voltage: 0 v to vref dedicated for generating comparator c reference voltage ? daa 2 channels 8-bit resolution output voltage: 0 v to vref can be output externally and used as comparator c reference vol tage safety memory protection unit (mpu) ? protection area: eight areas (max.) can be specified in the ran ge from 0000 0000h to ffff ffffh. ? minimum protection unit: 16 bytes ? reading from, writing to, and enabling the execution access can be specified for each area. ? an address exception occurs when the detected access is not in the permitted area. register write protection function ? protects important registers from being overwritten for in case a program runs out of control. crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit unit s ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-first or msb-first communications is selectable. main clock oscillation stop function ? main clock oscillation stop detection: available clock frequency accuracy measurement circuit (cac) ? monitors the clock output from t he main clock oscillator, high- speed on-chip oscillator, low-speed on- chip oscillator, the pll frequency synthesizer, iwdt-dedicated on-chip oscillator, and pclkb. data operation circuit (doc) the function to compare, add, or su btract 16-bit data power supply voltages/operating frequencies vcc = 2.7 to 5.5 v: 80 mhz packages 100-pin lfqfp 0.5 mm pitch 80-pin lqfp 0.65 mm pitch 80-pin lfqfp 0.5 mm pitch 64-pin lfqfp 0.5 mm pitch on-chip debugging system e1 emulator (fine interface) table 1.1 outline of specifications (4/4) classification module/function description
r01ds0257ej0200 rev.2.00 page 6 of 133 apr 14, 2017 rx24t group 1. overview table 1.2 comparison of functions for different packages module/functions rx24t group chip version b chip version a 100 pins 100 pins 80 pins 64pins memory rom 512 k/384 k/ 256 kbytes 256 k/128 kbytes ram 32 kbytes 16 kbytes e2 dataflash 8 kbytes interrupts external interrupts nmi, irq0 to irq7 dtc data transfer controller (dtca) available timers multi-function timer pulse unit 3 (mtu3d) 9 channels general pwm timer (gptb) 4 channels not supported port output enable 3 (poe3b) not supported available port output enable 3 (poe3a) available not supported 8-bit timer (tmr) 2 channels 4 units compare match timer (cmt) 2 channels 2 units independent watchdog timer (iwdta) available communic ations serial communications interfaces (scig) [including simple i 2 c and simple spi] 3 channels (sci1, sci5, sci6) i 2 c bus interface (riica) 1 channel serial peripheral interface (rspib) 1 channel can module (rscan) 1 channel not supported 12-bit a/d converter (s12adf) (internal high-precision channel) 5 channels 2 units, 12 channels 1 unit (4 channels 2 units, 12 channels 1 unit) 5 channels 2 units, 7 channels 1 unit (4 channels 2 units, 7 channels 1 unit) 3 channels 1 unit, 4 channels 1 unit, 5 channels 1 unit (3 channels 1 unit, 3 channels 1 unit, 5 channels 1 unit) 3 channels simultaneous sampling 3 channels/unit 1 programmable gain amplifier 1 channel/unit 0, 3 channels/unit 1 comparator c (cmpc) 4 channels without reference voltage external input with reference voltage external input 8-bit d/a converter (da) not supported available 8-bit d/a converter (daa) available not supported crc calculator (crc) available packages 100-pin lfqfp 100-pin lfqfp 80-pin lfqfp/lqfp 64-pin lfqfp
r01ds0257ej0200 rev.2.00 page 7 of 133 apr 14, 2017 rx24t group 1. overview 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product part no., memory capacity, and p ackage type. note: the part numbers for orders above are used for products in mass production or under development when this manual is issue d. refer to the renesas electronics corporation website for the latest part numbers. table 1.3 list of products group part no. part no. (for orders) package rom capacity ram capacity e2 dataflash operating frequency (max.) chip version rx24t r5f524teadfp r5f524teadfp#31 plqp0100kb-b 512 kbytes 32 kbytes 8 kbytes 80 mhz b r5f524tcadfp r5f524tcadfp#31 plqp0100kb-b 384 kbytes r5f524tbadfp r5f524tbadfp#31 plqp0100kb-b 256 kbytes r5f524taadfp r5f524taadfp#31 plqp0100kb-b 256 kbytes 16 kbytes 8 kbytes 80 mhz a r5f524taadff r5f524taadff#31 plqp0080ja-a r5f524taadfn r5f524taadfn#31 plqp0080kb-b r5f524taadfm r5f524taadfm#31 plqp0064kb-c r5f524t8adfp r5f524t8adfp#31 plqp0100kb-b 128 kbytes R5F524T8ADFF R5F524T8ADFF#31 plqp0080ja-a r5f524t8adfn r5f524t8adfn#31 plqp0080kb-b r5f524t8adfm r5f524t8adfm#31 plqp0064kb-c
r01ds0257ej0200 rev.2.00 page 8 of 133 apr 14, 2017 rx24t group 1. overview figure 1.1 how to read th e product part number r5f 52 4teadfp#31 product identification code packaging/external pin surface treatment (lead-free) #3: tray/sn (tin) only package type, number of pins, and pin pitch fp: lfqfp/100/0.50 ff: lqfp/80/0.65 fn: lfqfp/80/0.50 fm: lfqfp/64/0.5 d: operating peripheral temperature: C40 to +85c a: 5 v rom/ram/e2 dataflash capacity [chip version b] e: 512 kbytes/32 kbytes/8 kbytes c: 384 kbytes/32 kbytes/8 kbytes b: 256 kbytes/32 kbytes/8 kbytes [chip version a] a: 256 kbytes/16 kbytes/8 kbytes 8: 128 kbytes/16 kbytes/8 kbytes group name 4t:rx24t group series name rx200 series type of memory f: flash memory version renesas mcu renesas semiconductor product
r01ds0257ej0200 rev.2.00 page 9 of 133 apr 14, 2017 rx24t group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram clock generation circuit rx cpu ram rom port 0 port 1 port 3 port 4 dtca icub port a port b port 2 port 7 port 9 port d port e mtu3d 9 channels mpu operand bus instruction bus internal main bus 1 internal main bus 2 e2 dataflash port 5 port 6 port 8 gptb 4 channels cac doc 8-bit d/a converter 2 channels comparator c 4 channels 12-bit a/d converter 12 channels (unit 2) 12-bit a/d converter 5 channels (unit 1) sample and hold circuit 3 channels programmable gain amplifier 3 channels 12-bit a/d converter 5 channels (unit 0) programmable gain amplifier 1 channel cmt 2 channels (unit 1) cmt 2 channels (unit 0) tmr 2 channels (unit 3) tmr 2 channels (unit 2) tmr 2 channels (unit 1) tmr 2 channels (unit 0) rscan 1 channel riica 1 channel rspib 1 channel scig 3 channels crc iwdta internal peripheral buses 1 to 6 poe3b, poe3a mtu3d: multi-function timer pulse unit 3 gptb: general pwm timer icub: interrupt controller dtca: data transfer controller iwdta: independent watchdog timer crc: crc (cyclic redundancy check) calculator scig: serial communications interface rspib: serial peripheral interface riica: i 2 c bus interface rscan: can module poe3b, poe3a: port output enable 3 tmr: 8-bit timer cmt: compare match timer doc: data operation circuit cac: clock frequency accuracy measurement circuit mpu: memory protection unit
r01ds0257ej0200 rev.2.00 page 10 of 133 apr 14, 2017 rx24t group 1. overview 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1/4) classifications pin name i/o description power supply vcc power supply p in. connect it to the system powe r supply. vcl connect this pin to the vss pin via the 4.7 f smoothing ca pacitor used to stabilize the internal power supply. place the capacitor close to the pin. vss ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal. an external clock can be input through the extal pin. extal input operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. system control res# input reset pin. this mcu enters the reset sta te when this signal goes low. cac cacref input input pin for the clock frequency accuracy measur ement circuit. on-chip emulator fined i/o fine interface pin. interrupts nmi input non-maskable interrupt request pin. irq0 to irq7 input interrupt request pins. multi-function timer pulse unit 3 (mtu3d) mtioc0a, mtioc0b, mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output /pwm output pins. mtioc0a#, mtioc0b#, mtioc0c#, mtioc0d# i/o the tgra0 to tgrd0 input capture inverted input/output compa re inverted output/pwm inverted output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. mtioc1a#, mtioc1b# i/o the tgra1 and tgrb1 input capture inverted input/output compare inverted output/pwm inverted output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. mtioc2a#, mtioc2b# i/o the tgra2 and tgrb2 input capture inverted input/output compare inverted output/pwm inverted output pins. mtioc3a, mtioc3b, mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output /pwm output pins. mtioc3a#, mtioc3b#, mtioc3c#, mtioc3d# i/o the tgra3 to tgrd3 input capture inverted input/output compa re inverted output/pwm inverted output pins. mtioc4a, mtioc4b, mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output /pwm output pins. mtioc4a#, mtioc4b#, mtioc4c#, mtioc4d# i/o the tgra4 to tgrd4 input capture inverted input/output compa re inverted output/pwm inverted output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input ca pture input/external pulse input pins. mtic5u#, mtic5v#, mtic5w# input the tgru5, tgrv5, and tgrw5 input capture inverted input/e xternal pulse inverted input pins. mtioc6a, mtioc6b, mtioc6c, mtioc6d i/o the tgra6 to tgrd6 input capture input/output compare output /pwm output pins. mtioc6a#, mtioc6b#, mtioc6c#, mtioc6d# i/o the tgra6 to tgrd6 input capture inverted input/output compa re inverted output/pwm inverted output pins. mtioc7a, mtioc7b, mtioc7c, mtioc7d i/o the tgra7 to tgrd7 input capture input/output compare output /pwm output pins. mtioc7a#, mtioc7b#, mtioc7c#, mtioc7d# i/o the tgra7 to tgrd7 input capture inverted input/output compa re inverted output/pwm inverted output pins. mtioc9a, mtioc9b, mtioc9c, mtioc9d i/o the tgra9 to tgrd9 input capture input/output compare output /pwm output pins.
r01ds0257ej0200 rev.2.00 page 11 of 133 apr 14, 2017 rx24t group 1. overview multi-function timer pulse unit 3 (mtu3d) mtioc9a#, mtioc9b#, mtioc9c#, mtioc9d# i/o the tgra9 to tgrd9 input capture inverted input/output compa re inverted output/pwm inverted output pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. mtclka#, mtclkb#, mtclkc#, mtclkd# input inverted input pins fo r the external clock. adsm0, adsm1 output a/d trigger output pins. general pwm timer (gptb) gtioc0a, gtioc0b i/o the gpt0.gtg ra and gpt0.gtgrb input capture input/output compare output/pwm output pins gtioc0a#, gtioc0b# i/o the gpt0.gtgra and gpt0.gtgrb input captur e inverted input/output compare inverted output/pwm inverted output pins gtioc1a, gtioc1b i/o the gpt1.gtg ra and gpt1.gtgrb input capture input/output compare output/pwm output pins gtioc1a#, gtioc1b# i/o the gpt1.gtgra and gpt1.gtgrb input captur e inverted input/output compare inverted output/pwm inverted output pins gtioc2a, gtioc2b i/o the gpt2.gtg ra and gpt2.gtgrb input capture input/output compare output/pwm output pins gtioc2a#, gtioc2b# i/o the gpt2.gtgra and gpt2.gtgrb input captur e inverted input/output compare inverted output/pwm inverted output pins gtioc3a, gtioc3b i/o the gpt3.gtg ra and gpt3.gtgrb input capture input/output compare output/pwm output pins gtioc3a#, gtioc3b# i/o the gpt3.gtgra and gpt3.gtgrb input captur e inverted input/output compare inverted output/pwm inverted output pins gtetrg input external trigger input pin for gpt0 to gpt3 gteclka, gteclkb, gteclkc, gteclkd input input pins a to d for the external clock gtadsm0, gtadsm1 output a/d conv ersion start request monitoring o utput pins 8-bit timer (tmr) tmo0 to tmo7 output compare match output pins. tmci0 to tmci7 input input pins for the external clock to be inpu t to the counter. tmri0 to tmri7 input counter reset input pins. port output enable 3 (poe3b, poe3a) poe0#, poe4#, poe8#, poe10#, poe11#, poe12# input input pins for request signal s to switch the mtu and gpt p ins between the high impedance state or operation as general i/o port pins serial communications interface (scig) ? asynchronous mode/clock synchronous mode sck1, sck5, sck6 i/o input/output pins for the clock. rxd1, rxd5, rxd6 input input pins for received data. txd1, txd5, txd6 output output pins for transmitted data. cts1#, cts5#, cts6# input input pins for controlling the start of transmission and reception. rts1#, rts5#, rts6# output output pins for controlling the start of transmission and reception. ? simple i 2 c mode sscl1, sscl5, sscl6 i/o input/output pins for the i 2 c clock. ssda1, ssda5, ssda6 i/o input/output pins for the i 2 c data. ? simple spi mode sck1, sck5, sck6 i/o input/output pins for the clock. smiso1, smiso5, smiso6 i/o input/output pins for slave transmit d ata. smosi1, smosi5, smosi6 i/o input/output pins for master transmit data. ss1#, ss5#, ss6# input chip-select input pins. table 1.4 pin functions (2/4) classifications pin name i/o description
r01ds0257ej0200 rev.2.00 page 12 of 133 apr 14, 2017 rx24t group 1. overview i 2 c bus interface (riica) scl0 i/o input/output pin for i 2 c bus interface clocks. bus can be directly driven by the n-channel open drain output. sda0 i/o input/output pin for i 2 c bus interface data. bus c an be directly driven by the n-channel open drain output. serial peripheral interface (rspib) rspcka i/o input/output pin for the rspi clock. mosia i/o input/output pin for transmitting data from the rspi ma ster. misoa i/o input/output pin for transmitting data from the rspi sl ave. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rsp i. can module (rscan) crxd0 input input pin ctxd0 output output pin 12-bit a/d converter (s12adf) an000 to an003, an016, an100 to an103, an116, an200 to an211 input input pins for the analog si gnals to be processed by the a /d converter. adst0, adst1, adst2 output output pins for a/d conversion status. adtrg0#, adtrg1#, adtrg2# input input pins for the external trigger signals that start the a/d conversion. 8-bit d/a converter (daa) da0, da1 output output pins for the analog signals to be processed by the d/a converter comparator c (cmpc) comp0 to comp3 output comparator detection result output pins. cvrefc0, cvrefc1 input analog reference voltage supply pins for c omparator c. cmpc00 to cmpc03 input analog input pin for cmpc0 cmpc10 to cmpc13 input analog input pin for cmpc1 cmpc20 to cmpc23 input analog input pin for cmpc2 cmpc30 to cmpc33 input analog input pin for cmpc3 analog power supply avcc0 analog power supply and re ference power supply pin for 12 -bit a/d converter unit 0. connect the avcc0 pin to avcc1, avcc2, or vre f when 12-bit a/d converter unit 0 is not used. avss0 analog ground and reference ground pin for 12-bit a/d con verter unit 0. connect the avss0 pin to avss1 or avss2 when 12-bit a/d convert er unit 0 is not used. avcc1 analog power supply and re ference power supply pin for 12 -bit a/d converter unit 1. connect the avcc1 pin to avcc0, avcc2, or vre f when 12-bit a/d converter unit 1 is not used. avss1 analog ground and reference ground pin for 12-bit a/d con verter unit 1. connect the avss1 pin to avss0 or avss2 when 12-bit a/d convert er unit 1 is not used. avcc2 analog power supply and re ference power supply pin for 12 -bit a/d converter unit 2. connect the avcc2 pin to avcc0, avcc1, or vre f when 12-bit a/d converter unit 2 is not used. avss2 analog ground and reference ground pin for 12-bit a/d con verter unit 2. analog ground pin for comparator c and 8-bit d/a converter. con nect the avss2 pin to avss0 or avss1 when 12-bit a/d converter unit 2, comparator c and 8-bit d/a converter are not used. vref analog power supply pin for comparator c and 8-bit d/a con verter. for the 64-pin lfqfp package, the vref pin is internally connected to a vcc2 and is shared. connect the vref pin to avcc0, avcc1, or avcc2 w hen comparator c and 8-bit d/a converter are not used. table 1.4 pin functions (3/4) classifications pin name i/o description
r01ds0257ej0200 rev.2.00 page 13 of 133 apr 14, 2017 rx24t group 1. overview note: when the a/d converter, d/a converter, and comparator c ar e not used, connect the avcc0, avcc1, avcc2, and vref pins to vcc, and connect the avss0, avss1 and avss2 pins to vss, res pectively. i/o ports p00 to p02 i/o 3-bit input/output pins. p10, p11 i/o 2-bit input/output pins. p20 to p24 i/o 5-bit input/output pins. p30 to p33, p36, p37 i/o 6-bit input/output pins. p40 to p47 i/o 8-bit input/output pins. p50 to p55 i/o 6-bit input/output pins. p60 to p65 i/o 6-bit input/output pins. p70 to p76 i/o 7-bit input/output pins. p80 to p82 i/o 3-bit input/output pins. p90 to p96 i/o 7-bit input/output pins. pa0 to pa5 i/o 6-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe5 i/o 6-bit input/output pins (pe2: input). table 1.4 pin functions (4/4) classifications pin name i/o description
r01ds0257ej0200 rev.2.00 page 14 of 133 apr 14, 2017 rx24t group 1. overview 1.5 pin assignments figure 1.3 to figure 1.6 shows the pin assignments. table 1.5 to table 1.8 shows the lists of pins and pin functions. figure 1.3 pin assignments of the 100-pin lfqfp (chip version a and b) note: this figure indicates the power supply pins and i/o port p ins. for the pin configuration, refer to list of pins and pin functions (100-pin lfqfp, chip version a) or (100-pin lfqfp, chip version b). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 rx24t group plqp0100kb-b (100-pin lfqfp) (upper perspective view) pe5 vss p00 vcl md p01 pe4 pe3 res# xtal/p37 vss extal/p36 pe2 pe1 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd0 p02 vcc pd1 p90 p92 p93 p94 p95 vss p96 vcc pa0 pa1 pa2 pa3 pa4 pb0 pb1 pb2 pb3 vss pb4 vcc pb5 pb6 pb7 p91 pa5 p62 avss2 vref avcc2 p64 p65 p20 p21 p22 p23 p24 p30 vss vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 p63 p31 p55 p54 p53 p52 p51 p50 p47 p46 p45 p44 p43 p42 p40 avcc1 avcc0 avss0 avss1 p82 p81 p80 p11 p60 p41 p61 p10
r01ds0257ej0200 rev.2.00 page 15 of 133 apr 14, 2017 rx24t group 1. overview figure 1.4 pin assignments of the 80-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p55 p54 p53 p52 p51 p50 p47 p46 p45 p43 p42 p41 p40 avcc1 avcc0 avss0 avss1 p11 p44 p90 p91 p92 p93 p94 p95 vss p96 vcc pa5 pb0 pb1 pb2 pb3 vss pb4 vcc pb5 pb6 pa3 p62 avss2 vref avcc2 p20 p21 p22 p23 p24 p30 vss p31 vcc p71 p72 p73 p74 p75 p70 vss p00 vcl md p01 pe4 pe3 res# p37/xtal vss p36/extal pe2 pd7 pd6 pd5 pd4 pd3 p02 vcc p10 rx24t group plqp0080ja-a (80-pin lqfp) (upper perspective view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pd2 p76 note: this figure indicates the power supply pins and i/o port p ins. for the pin configuration, refer to list of pins and pin functi ons (80-pin lqfp/lfqfp).
r01ds0257ej0200 rev.2.00 page 16 of 133 apr 14, 2017 rx24t group 1. overview figure 1.5 pin assignments of the 80-pin lfqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p55 p54 p53 p52 p51 p50 p47 p46 p45 p43 p42 p41 p40 avcc1 avcc0 avss0 avss1 p11 p44 p90 p91 p92 p93 p94 p95 vss p96 vcc pa5 pb0 pb1 pb2 pb3 vss pb4 vcc pb5 pb6 pa3 p62 avss2 vref avcc2 p20 p21 p22 p23 p24 p30 vss p31 vcc p71 p72 p73 p74 p75 p70 vss p00 vcl md p01 pe4 pe3 res# p37/xtal vss p36/extal pe2 pd7 pd6 pd5 pd4 pd3 p02 vcc p10 rx24t group plqp0080kb-b (80-pin lfqfp) (upper perspective view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pd2 p76 note: this figure indicates t he power supply pins and i/o port pins. for the pin configuration, refer to list of pins and pin functi ons (80-pin lqfp/lfqfp).
r01ds0257ej0200 rev.2.00 page 17 of 133 apr 14, 2017 rx24t group 1. overview figure 1.6 pin assignments of the 64-pin lfqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx24t group plqp0064kb-c (64-pin lfqfp) (upper perspective view) p54 p53 p52 p51 p50 p46 p45 p44 p42 p41 p40 avcc1 avcc0 avss0 avss1 p11 avss2 avcc2/vref p21 p22 p23 p24 p30 vss p31 vcc p70 p71 p72 p73 p74 p75 p76 p90 p91 p92 p93 p94 p95 vss p96 vcc pb1 pb2 pb3 pb4 pb5 pb6 p02 p00 vcl md p01 res# p37/xtal vss p36/extal vcc pe2 pd7 pd6 pd5 pd4 pd3 this figure indicates the power supply pins and i/o port pins. for the pin configuration, refer to list of pins and pin functi ons (64-pin lfqfp). note:
r01ds0257ej0200 rev.2.00 page 18 of 133 apr 14, 2017 rx24t group 1. overview table 1.5 list of pins and pin functions (100-pin lfqfp, chip ve rsion b) (1/3) pin no. power supply, clock, system control i/o port timers (tmr, mtu, poe, cac, gpt) communications (sci, rspi, riic, rscan) others 1pe5 irq0 2 p02 mtioc9d, mtioc9d# cts1#, rts1#, ss1# irq5, adst0 3 vss 4p00 irq2, adst1 5vcl 6md fined 7 p01 poe12# irq4, adst2 8 pe4 mtclkc, mtclkc#, poe10# irq1 9 pe3 mtclkd, mtclkd#, poe11# irq2 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 pe2 poe10# nmi 16 pe1 mtioc9d, mtioc9d#, tmo5 cts5#, rts5#, ss5#, ssla3 17 pe0 mtioc9b, mtioc9b#, tmci1, tmci5 rxd5, smiso5, sscl5, ssla2 18 pd7 mtioc9a, mtioc9a#, tmri1, tmri5, gtioc3a, gtioc3a# txd5, smosi5, ssda5, ssla1 19 pd6 mtioc9c, mtioc9c#, tmo1, gtioc3b, gtioc3b# cts1#, rts1#, ss1#, ssla0 irq5, adst0 20 pd5 tmri0, tmri6, gteclka rxd1, smiso1, sscl1 irq3 21 pd4 tmci0, tmci6, gteclkb sck1 irq2 22 pd3 tmo0, gteclkc txd1, smosi1, ssda1 23 pd2 tmci1, tmo4, gtioc0a, gtioc0a# sck5, mosia 24 pd1 tmo2, gtioc0b, gtioc0b# misoa 25 pd0 tmo6, gtioc1a, gtioc1a# rspcka 26 pb7 gtioc1b, gtioc1b# sck5 27 pb6 gtioc2a, gtioc2a# rxd5, smiso5, sscl5 irq5 28 pb5 gtioc2b, gtioc2b# txd5, smosi5, ssda5 29 vcc 30 pb4 poe8#, gtetrg, gteclkd cts5#, rts5#, ss5# irq3 31 vss 32 pb3 mtioc0a, mtioc0a#, cacref sck6, rspcka 33 pb2 mtioc0b, mtioc0b#, tmri0, adsm0 txd6, smosi6, ssda6, sda0 34 pb1 mtioc0c, mtioc0c#, tmci0, adsm1 rxd6, smiso6, sscl6, scl0 35 pb0 mtioc0d, mtioc0d#, tmo0 txd6, smosi6, ssda6, mosia adtrg2# 36 pa5 mtioc1a, mtioc1a#, tmci3 rxd6, smiso6, sscl6, misoa irq1, ad trg1# 37 pa4 mtioc1b, mtioc1b#, tmci7 sck6, rspcka adtrg0# 38 pa3 mtioc2a, mtioc2a#, tmri7, gtadsm0 ssla0 39 pa2 mtioc2b, mtioc2b#, tmo7, gtadsm1 cts6#, rts6#, ss6#, ssla1 40 pa1 mtioc6a, mtioc6a#, tmo4 ssla2, crxd0 adtrg0# 41 pa0 mtioc6c, mtioc6c#, tmo2 ssla3, ctxd0 42 vcc 43 p96 poe4# irq4 44 vss 45 p95 mtioc6b, mtioc6b# 46 p94 mtioc7a, mtioc7a# 47 p93 mtioc7b, mtioc7b# 48 p92 mtioc6d, mtioc6d# 49 p91 mtioc7c, mtioc7c# 50 p90 mtioc7d, mtioc7d# 51 p76 mtioc4d, mtioc4d#, gtioc2b, gtioc2b#
r01ds0257ej0200 rev.2.00 page 19 of 133 apr 14, 2017 rx24t group 1. overview 52 p75 mtioc4c, mtioc4c#, gtioc1b, gtioc1b# 53 p74 mtioc3d, mtioc3d#, gtioc0b, gtioc0b# 54 p73 mtioc4b, mtioc4b#, gtioc2a, gtioc2a# 55 p72 mtioc4a, mtioc4a#, gtioc1a, gtioc1a# 56 p71 mtioc3b, mtioc3b#, gtioc0a, gtioc0a# 57 p70 poe0# irq5 58 p33 mtioc3a, mtioc3a#, mtclka, mtclka#, tmo0 ssla3 59 p32 mtioc3c, mtioc3c#, mtclkb, mtclkb#, tmo6 ssla2 60 vcc 61 p31 mtioc0a, mtioc0a#, mtclkc, mtclkc#, tmri6 ssla1 irq6 62 vss 63 p30 mtioc0b, mtioc0b#, mtclkd, mtclkd#, tmci6 ssla0 irq7, comp3 64 p24 mtic5u, mtic5u#, tm ci2, tmo6 rspcka comp0, da0 65 p23 mtic5v, mtic5v#, tmo 2, cacref mosia comp1, da1 66 p22 mtic5w, mtic5w#, tmri2, tmo4 misoa adtrg2#, comp2 67 p21 mtclka, mtclka#, mtioc9a, mtioc9a#, tmci4 irq6, adtrg1#, an116 68 p20 mtclkb, mtclkb#, mtioc9c, mtioc9c#, tmri4 irq7, adtrg0#, an016 69 p65 an205 70 p64 an204 71 avcc2 72 vref 73 avss2 74 p63 an203, irq7 75 p62 an202, irq6 76 p61 an201, irq5 77 p60 an200, irq4 78 p55 an211, irq3 79 p54 an210, irq2 80 p53 an209, irq1 81 p52 an208, irq0 82 p51 an207 83 p50 an206 84 p47 an103 85 p46 an102, cmpc12, cmpc13, cmpc30, cmpc31 86 p45 an101, cmpc02, cmpc03, cmpc20, cmpc21 87 p44 an100, cmpc10, cmpc11, cmpc32, cmpc33 88 p43 an003 89 p42 an002 90 p41 an001 91 p40 an000, cmpc00, cmpc01, cmpc22, cmpc23 92 avcc1 93 avcc0 table 1.5 list of pins and pin functions (100-pin lfqfp, chip ve rsion b) (2/3) pin no. power supply, clock, system control i/o port timers (tmr, mtu, poe, cac, gpt) communications (sci, rspi, riic, rscan) others
r01ds0257ej0200 rev.2.00 page 20 of 133 apr 14, 2017 rx24t group 1. overview 94 avss0 95 avss1 96 p82 mtic5u, mtic5u#, tmo4 sck6 97 p81 mtic5v, mtic5v#, tmci4 txd6, smosi6, ssda6 98 p80 mtic5w, mtic5w#, tmri4 rxd6, smiso6, sscl6 99 p11 mtioc3a, mtioc3a#, mtclkc, mtclkc#, tmo3 irq1 100 p10 mtioc9b, mtioc9b#, mtclkd, mtclkd#, tmri3, poe12# cts6#, rts6#, ss6# irq0 table 1.5 list of pins and pin functions (100-pin lfqfp, chip ve rsion b) (3/3) pin no. power supply, clock, system control i/o port timers (tmr, mtu, poe, cac, gpt) communications (sci, rspi, riic, rscan) others
r01ds0257ej0200 rev.2.00 page 21 of 133 apr 14, 2017 rx24t group 1. overview table 1.6 list of pins and pin functions (100-pin lfqfp, chip ve rsion a) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (sci, rspi, riic) others 1pe5 irq0 2 p02 mtioc9d cts1#, rts1#, ss1# irq5, adst0 3 vss 4p00 irq2, adst1 5vcl 6md fined 7 p01 poe12# irq4, adst2 8 pe4 mtclkc, poe10# irq1 9 pe3 mtclkd, poe11# irq2 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 pe2 poe10# nmi 16 pe1 mtioc9d, tmo5 cts5#, rts5#, ss5#, ssla3 17 pe0 mtioc9b, tmci1, tmci5 ssla2 18 pd7 mtioc9a, tmri1, tmri5 ssla1 19 pd6 mtioc9c, tmo1 cts1#, rts1#, ss1#, ssla0 irq5, adst0 20 pd5 tmri0, tmri6 rxd1, smiso1, sscl1 irq3 21 pd4 tmci0, tmci6 sck1 irq2 22 pd3 tmo0 txd1, smosi1, ssda1 23 pd2 tmci1, tmo4 sck5, mosia 24 pd1 tmo2 misoa 25 pd0 tmo6 rspcka 26 pb7 sck5 27 pb6 rxd5, smiso5, sscl5 irq5 28 pb5 txd5, smosi5, ssda5 29 vcc 30 pb4 poe8# cts5#, rts5#, ss5# irq3 31 vss 32 pb3 mtioc0a, cacref sck6, rspcka 33 pb2 mtioc0b, tmri0, adsm0 txd6, smosi6, ssda6, sda0 34 pb1 mtioc0c, tmci0, adsm1 rxd6, smiso6, sscl6, scl0 35 pb0 mtioc0d, tmo0 txd6, smosi6, ssda6, mosia adtrg2# 36 pa5 mtioc1a, tmci3 rxd6, smiso6, sscl6, misoa irq1, adtrg1# 37 pa4 mtioc1b, tmci7 sck6, rspcka adtrg0# 38 pa3 mtioc2a, tmri7 ssla0 39 pa2 mtioc2b, tmo7 cts6#, rts6#, ss6#, ssla1 40 pa1 mtioc6a, tmo4 ssla2 adtrg0# 41 pa0 mtioc6c, tmo2 ssla3 42 vcc 43 p96 poe4# irq4 44 vss 45 p95 mtioc6b 46 p94 mtioc7a 47 p93 mtioc7b 48 p92 mtioc6d 49 p91 mtioc7c 50 p90 mtioc7d 51 p76 mtioc4d 52 p75 mtioc4c 53 p74 mtioc3d 54 p73 mtioc4b
r01ds0257ej0200 rev.2.00 page 22 of 133 apr 14, 2017 rx24t group 1. overview 55 p72 mtioc4a 56 p71 mtioc3b 57 p70 poe0# irq5 58 p33 mtioc3a, mtclka, tmo0 ssla3 59 p32 mtioc3c, mtclkb, tmo6 ssla2 60 vcc 61 p31 mtioc0a, mtclkc, tmri6 ssla1 irq6 62 vss 63 p30 mtioc0b, mtclkd, tmci6 ssla0 irq7, comp3 64 p24 mtic5u, tmci2, tmo6 rspcka comp0 65 p23 mtic5v, tmo2, cacref mosia comp1 66 p22 mtic5w, tmri2, tmo4 misoa adtrg2#, comp2 67 p21 mtclka, mtioc9a, tmci4 irq6, adtrg1#, an116, cvrefc1 68 p20 mtclkb, mtioc9c, tmri4 irq7, adtrg0#, an016, cvrefc0 69 p65 an205 70 p64 an204 71 avcc2 72 vref 73 avss2 74 p63 an203, irq7 75 p62 an202, irq6 76 p61 an201, irq5 77 p60 an200, irq4 78 p55 an211, irq3 79 p54 an210, irq2 80 p53 an209, irq1 81 p52 an208, irq0 82 p51 an207 83 p50 an206 84 p47 an103 85 p46 an102, cmpc12, cmpc13, cmpc30, cmpc31 86 p45 an101, cmpc02, cmpc03, cmpc20, cmpc21 87 p44 an100, cmpc10, cmpc11, cmpc32, cmpc33 88 p43 an003 89 p42 an002 90 p41 an001 91 p40 an000, cmpc00, cmpc01, cmpc22, cmpc23 92 avcc1 93 avcc0 94 avss0 95 avss1 96 p82 mtic5u, tmo4 sck6 97 p81 mtic5v, tmci4 txd6, smosi6, ssda6 98 p80 mtic5w, tmri4 rxd6, smiso6, sscl6 99 p11 mtioc3a, mtclkc, tmo3 irq1 100 p10 mtioc9b, mtclkd, tmri3, poe12# cts6#, rts6#, ss6# irq0 table 1.6 list of pins and pin functions (100-pin lfqfp, chip ve rsion a) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (sci, rspi, riic) others
r01ds0257ej0200 rev.2.00 page 23 of 133 apr 14, 2017 rx24t group 1. overview table 1.7 list of pins and pin functions (80-pin lqfp/lfqfp) (1/ 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (sci, rspi, riic) others 1 p02 mtioc9d cts1#, rts1#, ss1# irq5, adst0 2 vss 3p00 irq2, adst1 4vcl 5md fined 6 p01 poe12# irq4, adst2 7 pe4 mtclkc, poe10# irq1 8 pe3 mtclkd, poe11# irq2 9 res# 10 xtal p37 11 vss 12 extal p36 13 vcc 14 pe2 poe10# nmi 15 pd7 mtioc9a, tmri1, tmri5 ssla1 16 pd6 mtioc9c, tmo1 cts1#, rts1#, ss1#, ssla0 irq5, adst0 17 pd5 tmri0, tmri6 rxd1, smiso1, sscl1 irq3 18 pd4 tmci0, tmci6 sck1 irq2 19 pd3 tmo0 txd1, smosi1, ssda1 20 pd2 tmci1, tmo4 sck5, mosia 21 pb6 rxd5, smiso5, sscl5 irq5 22 pb5 txd5, smosi5, ssda5 23 vcc 24 pb4 poe8# cts5#, rts5#, ss5# irq3 25 vss 26 pb3 mtioc0a, cacref sck6, rspcka 27 pb2 mtioc0b, tmri0, adsm0 txd6, smosi6, ssda6, sda0 28 pb1 mtioc0c, tmci0, adsm1 rxd6, smiso6, sscl6, scl0 29 pb0 mtioc0d, tmo0 txd6, smosi6, ssda6, mosia adtrg2# 30 pa5 mtioc1a, tmci3 rxd6, smiso6, sscl6, misoa irq1, adtrg1# 31 pa3 mtioc2a, tmri7 ssla0 32 vcc 33 p96 poe4# irq4 34 vss 35 p95 mtioc6b 36 p94 mtioc7a 37 p93 mtioc7b 38 p92 mtioc6d 39 p91 mtioc7c 40 p90 mtioc7d 41 p76 mtioc4d 42 p75 mtioc4c 43 p74 mtioc3d 44 p73 mtioc4b 45 p72 mtioc4a 46 p71 mtioc3b 47 p70 poe0# irq5 48 vcc
r01ds0257ej0200 rev.2.00 page 24 of 133 apr 14, 2017 rx24t group 1. overview 49 p31 mtioc0a, mtclkc, tmri6 ssla1 irq6 50 vss 51 p30 mtioc0b, mtclkd, tmci6 ssla0 irq7, comp3 52 p24 mtic5u, tmci2, tmo6 rspcka comp0 53 p23 mtic5v, tmo2, cacref mosia comp1 54 p22 mtic5w, tmri2, tmo4 misoa adtrg2#, comp2 55 p21 mtclka, mtioc9a, tmci4 irq6, adtrg1#, an116, cvrefc1 56 p20 mtclkb, mtioc9c, tmri4 irq7, adtrg0#, an016, cvrefc0 57 avcc2 58 vref 59 avss2 60 p62 an202, irq6 61 p55 an211, irq3 62 p54 an210, irq2 63 p53 an209, irq1 64 p52 an208, irq0 65 p51 an207 66 p50 an206 67 p47 an103 68 p46 an102, cmpc12, cmpc13, cmpc30, cmpc31 69 p45 an101, cmpc02, cmpc03, cmpc20, cmpc21 70 p44 an100, cmpc10, cmpc11, cmpc32, cmpc33 71 p43 an003 72 p42 an002 73 p41 an001 74 p40 an000, cmpc00, cmpc01, cmpc22, cmpc23 75 avcc1 76 avcc0 77 avss0 78 avss1 79 p11 mtioc3a, mtclkc, tmo3 irq1 80 p10 mtioc9b, mtclkd, tmri3, poe12# cts6#, rts6#, ss6# irq0 table 1.7 list of pins and pin functions (80-pin lqfp/lfqfp) (2/ 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (sci, rspi, riic) others
r01ds0257ej0200 rev.2.00 page 25 of 133 apr 14, 2017 rx24t group 1. overview table 1.8 list of pins and pin functions (64-pin lfqfp) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (sci, rspi, riic) others 1 p02 mtioc9d cts1#, rts1#, ss1# irq5, adst0 2p00 irq2, adst1 3vcl 4md fined 5 p01 poe12# irq4, adst2 6 res# 7xtal p37 8 vss 9 extal p36 10 vcc 11 pe2 poe10# nmi 12 pd7 mtioc9a, tmri1, tmri5 ssla1 13 pd6 mtioc9c, tmo1 cts1#, rts1#, ss1# 14 pd5 tmri0, tmri6 rxd1, smiso1, sscl1 15 pd4 tmci0, tmci6 sck1 irq2 16 pd3 tmo0 txd1, smosi1, ssda1 17 pb6 rxd5, smiso5, sscl5 irq5 18 pb5 txd5, smosi5, ssda5 19 pb4 poe8# cts5#, rts5#, ss5# irq3 20 pb3 mtioc0a, cacref sck6, rspcka 21 pb2 mtioc0b, tmri0, adsm0 txd6, smosi6, ssda6, sda0 22 pb1 mtioc0c, tmci0, adsm1 rxd6, smiso6, sscl6, scl0 23 vcc 24 p96 poe4# irq4 25 vss 26 p95 mtioc6b 27 p94 mtioc7a 28 p93 mtioc7b 29 p92 mtioc6d 30 p91 mtioc7c 31 p90 mtioc7d 32 p76 mtioc4d 33 p75 mtioc4c 34 p74 mtioc3d 35 p73 mtioc4b 36 p72 mtioc4a 37 p71 mtioc3b 38 p70 poe0# irq5 39 vcc 40 p31 mtioc0a, mtclkc, tmri6 ssla1 irq6 41 vss 42 p30 mtioc0b, mtclkd, tmci6 ssla0 irq7, comp3 43 p24 mtic5u, tmci2, tmo6 rspcka comp0 44 p23 mtic5v, tmo2, cacref mosia comp1 45 p22 mtic5w, tmri2, tmo4 misoa adtrg2#, comp2 46 p21 mtclka, mtioc9a, tmci4 irq6, adtrg1#, an116, cvrefc1 47 avcc2/vref 48 avss2 49 p54 an210, irq2 50 p53 an209, irq1 51 p52 an208, irq0 52 p51 an207 53 p50 an206
r01ds0257ej0200 rev.2.00 page 26 of 133 apr 14, 2017 rx24t group 1. overview 54 p46 an102, cmpc12, cmpc13, cmpc30, cmpc31 55 p45 an101, cmpc02, cmpc03, cmpc20, cmpc21 56 p44 an100, cmpc10, cmpc11, cmpc32, cmpc33 57 p42 an002 58 p41 an001 59 p40 an000, cmpc00, cmpc01, cmpc22, cmpc23 60 avcc1 61 avcc0 62 avss0 63 avss1 64 p11 mtioc3a, mtclkc, tmo3 irq1 table 1.8 list of pins and pin functions (64-pin lfqfp) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (sci, rspi, riic) others
r01ds0257ej0200 rev.2.00 page 27 of 133 apr 14, 2017 rx24t group 2. cpu 2. cpu figure 2.1 shows register s et of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) c an be the interrupt stack pointe r (isp) or user stack pointer (usp), according to the value of the u bit in the psw. r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose register b31 b0 dsp instruction register b71 b0 acc0 (accumulator 0) acc1 (accumulator 1) usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) control register b31 b0 extb (exception table register)
r01ds0257ej0200 rev.2.00 page 28 of 133 apr 14, 2017 rx24t group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen 32-bit gene ral-purpose regist ers (r0 to r1 5). r0 to r15 can b e used as data registers or address registers. r0, a general-purpose register , also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw) . 2.2 control registers (1) interrupt stack pointer (isp) and user sta ck pointer (usp) the stack pointer (sp) can be either of tw o types, the interrup t stack pointer (isp) or the user st ack pointer (usp). whether the stack pointer operate s as the isp or usp depends on the value of the stack pointer select bit (u) in the processor status word (psw). set the isp or usp to a multiple of 4 to reduce th e number of c ycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) exception table register (extb) the exception table register (ex tb) specifies the address where the exception vector table starts. set the extb to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (3) interrupt table register (intb) the interrupt table register (intb) specifies the address where the interrupt vector table starts. set the intb to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (4) program counter (pc) the program counter (pc) indicates the address of the instructi on being executed. (5) processor status word (psw) the processor status word (psw) indicates the results of instru ction execution or the state of the cpu. (6) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interru pts. after a fast interrupt has been g enerated, the contents of the program counter (pc) are sa ved in the bpc register. (7) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to inter rupts. after a fast interrupt has been g enerated, the contents of the processor status word (psw) are saved in the bpsw. the allocation of bits in the bpsw c orresponds to that in the psw. (8) fast interrupt vect or register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a b ranch destination address when a fast interrupt has been generated.
r01ds0257ej0200 rev.2.00 page 29 of 133 apr 14, 2017 rx24t group 2. cpu (9) floating-point s tatus word (fpsw) the floating-point status word ( fpsw) indicates t he results of floating-point operations. when an exception handling enable bit (ej) enables the exceptio n handling (ej = 1), the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if the exception handl ing is masked (ej = 0), the occurrence of exception can be checked by r eading the fj flag a t the end of a series of processing. once the fj flag has been set to 1, this value is r etained until it i s cleared to 0 by software (j = x, u, z, o, or v). 2.3 accumulator the accumulator (acc0 or acc1) is a 72-bit register used for ds p instructions. the accumula tor is handled as a 96-bit register for reading and writing. at this time, when bits 95 to 72 of the accumulator are read, the value where the value of bit 71 is sign extended is read. writing to bits 95 to 72 of th e accumulator is ignored. acc0 is also used for the multiply and multiply-and-accumulate instr uctions; emul, emulu, fmul, mu l, and rmpa, in which case the prior value in acc0 is modified by execu tion of the instruction. use the mvtacgu, mvtachi, and mv taclo instructions for writing to the accumulator. the mvtacgu, mvtachi, and mvtaclo instructions write data to bits 95 to 64, the higher-order 32 bits ( bits 63 to 32), and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfacgu, mvfachi, mvfacmi, and mvfaclo instructions for reading data from t he accumulator. the mvfacgu, mvfachi, mvfacmi, and mvfaclo instructions read data f rom the guard bits (bits 95 to 64), higher- order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 1 6), and the lower-order 32 bits (bits 31 to 0), respectively.
r01ds0257ej0200 rev.2.00 page 30 of 133 apr 14, 2017 rx24t group 3. address space 3. address space 3.1 address space this mcu has a 4-gbyte address space, consisting of the range o f addresses from 0000 0000h to ffff ffffh . that is, linear access to an address space of up to 4 gbytes is possible , and this contains both program and data areas. figure 3.1 shows the memory maps.
r01ds0257ej0200 rev.2.00 page 31 of 133 apr 14, 2017 rx24t group 3. address space figure 3.1 memory map in each operating mode reserved area *3 on-chip rom (e2 dataflash) (read only) reserved area *3 reserved area *3 reserved area *3 0000 0000h 0008 0000h ffff ffffh single-chip mode *1 ram *2 on-chip rom (program rom) (read only) *2 0010 0000h peripheral i/o registers 0080 0000h fff8 0000h peripheral i/o registers peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0000 8000h 0010 2000h note 1. the address space in boot mode is the same as the addres s space in single-chip mode. note 2. the capacity of rom/ram differs depending on the product s. note: see table 1.3 list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) e2 dataflash (bytes) capacity address capacity address capacity address 512 k fff8 0000h to ffff ffffh 32 k 0000 0000h to 0000 7fffh 8 k 001 0 0000h to 0010 1fffh 384 k fffa 0000h to ffff ffffh 256 k fffc 0000h to ffff ffffh 256 k fffc 0000h to ffff ffffh 16 k 0000 0000h to 0000 3fffh 128 k fffe 0000h to ffff ffffh
r01ds0257ej0200 rev.2.00 page 32 of 133 apr 14, 2017 rx24t group 4. i/o registers 4. i/o registers this section provides information on the on-chip i/o register a ddresses and bit configuration. the information is given as shown below. notes on writing to r egisters are also given below . (1) i/o register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified according to module symbols. ? numbers of cycles for access indi cate numbers of cycles of the given base clock. ? among the internal i/o registe r area, addresses not listed in t he list of registers are res erved. reserved addresses must not be accessed. do not access these addresses; otherwise, the operation when acces sing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register, the cpu starts executing the s ubsequent instruction before completing i/o register write. this may cause the subsequent i nstruction to be executed before the post-update i/o register value is reflected on the operation. as described in the following ex amples, special care is require d for the cases in which the subsequent instruction must be executed after the post-update i /o register value is actually r eflected. [examples of cases re quiring special care] ? the subsequent instruction must be executed while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request e nable bit) cleared to 0. ? a wait instruction is executed im mediately after the preprocess ing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operation using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0257ej0200 rev.2.00 page 33 of 133 apr 14, 2017 rx24t group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instructi on should be executed after the write operations are entirely completed, only read the i/o register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were wr itten to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o r egisters, see table 4.1, list of i/o reg isters (address order) . the number of access cy cles to i/o register s is obtained by fol lowing equation. * 1 number of access cy cles to i/o registers = number of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral bus 1 to 6 the number of bus cycl es of internal peripheral bus 1 to 6 diff ers according to the register to be accessed. when peripheral functions connected to internal p eripheral bus 2 to 6 are accessed, the number of divided clock synchronization cycles is added. in the peripheral function unit, when the frequency ratio of ic lk is equal to or greater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pcl k (or fclk) has been added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access from the cpu does not conflict with the bus access from the different bus master (dtc). (4) restrictions in relation to rmpa and string-manipulation ins tructions the allocation of data to be handled by rmpa or string-manipula tion instructions to i/o registers is prohibited, and operation is not guaranteed if this restriction is not observed . (5) notes on sleep mode and mode transitions during sleep mode or mode transitions, do not write to the syst em control related registers (indicated by system in the module symbol column in table 4.1, list of i/o registers (address order) ).
r01ds0257ej0200 rev.2.00 page 34 of 133 apr 14, 2017 rx24t group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o regist ers (address order) (1/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0031h system memory wait cycle setting register memwait 8 8 3 ic lk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0034h system low-speed on-chip oscillator control register lo cocr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control regis ter ilococr 8 8 3 iclk 0008 0036h system high-speed on-chip oscillator control register h ococr 8 8 3 iclk 0008 0037h system high-speed on-chip oscillator control register 2 hococr2 8 8 3 iclk 0008 003ch system oscillation stabilization flag register oscovfsr 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostd cr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostds r88 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register mosc wtcr 8 8 3 iclk 0008 00a5h system high-speed on-chip oscillator wait control regi ster hocowtcr 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit status register lvd 1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit status register lvd 2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1000h flash rom cache enable register romce 16 16 3 iclk 0008 1004h flash rom cache invalidate register romciv 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 6400h mpu region-0 start page number register rspage0 32 32 1 ic lk 0008 6404h mpu region-0 end page number register repage0 32 32 1 iclk 0008 6408h mpu region-1 start page number register rspage1 32 32 1 ic lk 0008 640ch mpu region-1 end page number register repage1 32 32 1 iclk 0008 6410h mpu region-2 start page number register rspage2 32 32 1 ic lk 0008 6414h mpu region-2 end page number register repage2 32 32 1 iclk 0008 6418h mpu region-3 start page number register rspage3 32 32 1 ic lk 0008 641ch mpu region-3 end page number register repage3 32 32 1 iclk
r01ds0257ej0200 rev.2.00 page 35 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 6420h mpu region-4 start page number register rspage4 32 32 1 ic lk 0008 6424h mpu region-4 end page number register repage4 32 32 1 iclk 0008 6428h mpu region-5 start page number register rspage5 32 32 1 ic lk 0008 642ch mpu region-5 end page number register repage5 32 32 1 iclk 0008 6430h mpu region-6 start page number register rspage6 32 32 1 ic lk 0008 6434h mpu region-6 end page number register repage6 32 32 1 iclk 0008 6438h mpu region-7 start page number register rspage7 32 32 1 ic lk 0008 643ch mpu region-7 end page number register repage7 32 32 1 iclk 0008 6500h mpu memory-protection enable register mpen 32 32 1 iclk 0008 6504h mpu background access control register mpbac 32 32 1 iclk 0008 6508h mpu memory-protection error status-clearing register mp eclr 32 32 1 iclk 0008 650ch mpu memory-protection error status register mpests 32 32 1 iclk 0008 6514h mpu data memory-protection error address register mpdea 32 32 1 iclk 0008 6520h mpu region search address register mpsa 32 32 1 iclk 0008 6524h mpu region search operation register mpops 16 16 1 iclk 0008 6526h mpu region invalidation operation register mpopi 16 16 1 i clk 0008 6528h mpu instruction-hit region register mhiti 32 32 1 iclk 0008 652ch mpu data-hit region register mhitd 32 32 1 iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 7028h icu interrupt request register 040* 2 ir040 8 8 2 iclk 0008 7029h icu interrupt request register 041* 2 ir041 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7030h icu interrupt request register 048* 2 ir048 8 8 2 iclk 0008 7031h icu interrupt request register 049* 2 ir049 8 8 2 iclk 0008 7032h icu interrupt request register 050* 2 ir050 8 8 2 iclk 0008 7033h icu interrupt request register 051* 2 ir051 8 8 2 iclk 0008 7034h icu interrupt request register 052* 2 ir052 8 8 2 iclk 0008 7035h icu interrupt request register 053* 2 ir053 8 8 2 iclk 0008 7036h icu interrupt request register 054* 2 ir054 8 8 2 iclk 0008 7037h icu interrupt request register 055* 2 ir055 8 8 2 iclk 0008 7038h icu interrupt request register 056* 2 ir056 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703bh icu interrupt request register 059* 2 ir059 8 8 2 iclk 0008 703ch icu interrupt request register 060* 2 ir060 8 8 2 iclk 0008 703dh icu interrupt request register 061* 2 ir061 8 8 2 iclk 0008 703eh icu interrupt request register 062* 2 ir062 8 8 2 iclk 0008 703fh icu interrupt request register 063* 2 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (2/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 36 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 7062h icu interrupt request register 098* 2 ir098 8 8 2 iclk 0008 7063h icu interrupt request register 099* 2 ir099 8 8 2 iclk 0008 7064h icu interrupt request register 100* 2 ir100 8 8 2 iclk 0008 7065h icu interrupt request register 101* 2 ir101 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 7068h icu interrupt request register 104 ir104 8 8 2 iclk 0008 7069h icu interrupt request register 105 ir105 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706bh icu interrupt request register 107 ir107 8 8 2 iclk 0008 706ch icu interrupt request register 108 ir108 8 8 2 iclk 0008 706dh icu interrupt request register 109 ir109 8 8 2 iclk 0008 706eh icu interrupt request register 110 ir110 8 8 2 iclk 0008 706fh icu interrupt request register 111 ir111 8 8 2 iclk 0008 7070h icu interrupt request register 112 ir112 8 8 2 iclk 0008 7071h icu interrupt request register 113 ir113 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (3/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 37 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 708fh icu interrupt request register 143 ir143 8 8 2 iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk 0008 7099h icu interrupt request register 153 ir153 8 8 2 iclk 0008 709fh icu interrupt request register 159 ir159 8 8 2 iclk 0008 70a0h icu interrupt request register 160 ir160 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a3h icu interrupt request register 163 ir163 8 8 2 iclk 0008 70a4h icu interrupt request register 164 ir164 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a8h icu interrupt request register 168 ir168 8 8 2 iclk 0008 70a9h icu interrupt request register 169 ir169 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70ach icu interrupt request register 172 ir172 8 8 2 iclk 0008 70adh icu interrupt request register 173 ir173 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70bah icu interrupt request register 186 ir186 8 8 2 iclk 0008 70bbh icu interrupt request register 187 ir187 8 8 2 iclk 0008 70bch icu interrupt request register 188 ir188 8 8 2 iclk 0008 70bdh icu interrupt request register 189 ir189 8 8 2 iclk 0008 70beh icu interrupt request register 190 ir190 8 8 2 iclk 0008 70bfh icu interrupt request register 191 ir191 8 8 2 iclk 0008 70c0h icu interrupt request register 192 ir192 8 8 2 iclk 0008 70c1h icu interrupt request register 193 ir193 8 8 2 iclk 0008 70c2h icu interrupt request register 194 ir194 8 8 2 iclk 0008 70c3h icu interrupt request register 195 ir195 8 8 2 iclk 0008 70c4h icu interrupt request register 196 ir196 8 8 2 iclk 0008 70c5h icu interrupt request register 197 ir197 8 8 2 iclk 0008 70cah icu interrupt request register 202* 2 ir202 8 8 2 iclk 0008 70cbh icu interrupt request register 203* 2 ir203 8 8 2 iclk 0008 70cch icu interrupt request register 204* 2 ir204 8 8 2 iclk 0008 70cdh icu interrupt request register 205* 2 ir205 8 8 2 iclk 0008 70ceh icu interrupt request register 206* 2 ir206 8 8 2 iclk 0008 70cfh icu interrupt request register 207* 2 ir207 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (4/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 38 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 70d0h icu interrupt request register 208* 2 ir208 8 8 2 iclk 0008 70d1h icu interrupt request register 209* 2 ir209 8 8 2 iclk 0008 70d2h icu interrupt request register 210* 2 ir210 8 8 2 iclk 0008 70d3h icu interrupt request register 211* 2 ir211 8 8 2 iclk 0008 70d4h icu interrupt request register 212* 2 ir212 8 8 2 iclk 0008 70d5h icu interrupt request register 213* 2 ir213 8 8 2 iclk 0008 70d6h icu interrupt request register 214* 2 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215* 2 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216* 2 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217* 2 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70eeh icu interrupt request register 238* 2 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239* 2 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240* 2 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241* 2 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242* 2 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243* 2 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244* 2 ir244 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 711bh icu dtc transfer reques t enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc transfer reques t enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc transfer reques t enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc transfer reques t enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc transfer reques t enable register 031 dtcer031 8 8 2 iclk 0008 712dh icu dtc transfer reques t enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc transfer reques t enable register 046 dtcer046 8 8 2 iclk 0008 7130h icu dtc transfer request enable register 048* 2 dtcer048 8 8 2 iclk 0008 7131h icu dtc transfer request enable register 049* 2 dtcer049 8 8 2 iclk 0008 7132h icu dtc transfer request enable register 050* 2 dtcer050 8 8 2 iclk 0008 7133h icu dtc transfer request enable register 051* 2 dtcer051 8 8 2 iclk 0008 7135h icu dtc transfer request enable register 053* 2 dtcer053 8 8 2 iclk 0008 7136h icu dtc transfer request enable register 054* 2 dtcer054 8 8 2 iclk 0008 7137h icu dtc transfer request enable register 055* 2 dtcer055 8 8 2 iclk 0008 7138h icu dtc transfer request enable register 056* 2 dtcer056 8 8 2 iclk 0008 713bh icu dtc transfer request enable register 059* 2 dtcer059 8 8 2 iclk 0008 7140h icu dtc transfer reques t enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc transfer reques t enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc transfer reques t enable register 066 dtcer066 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (5/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 39 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 7143h icu dtc transfer reques t enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc transfer reques t enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc transfer reques t enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc transfer reques t enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc transfer reques t enable register 071 dtcer071 8 8 2 iclk 0008 7162h icu dtc transfer request enable register 098* 2 dtcer098 8 8 2 iclk 0008 7163h icu dtc transfer request enable register 099* 2 dtcer099 8 8 2 iclk 0008 7164h icu dtc transfer request enable register 100* 2 dtcer100 8 8 2 iclk 0008 7165h icu dtc transfer request enable register 101* 2 dtcer101 8 8 2 iclk 0008 7166h icu dtc transfer reques t enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc transfer reques t enable register 103 dtcer103 8 8 2 iclk 0008 7168h icu dtc transfer reques t enable register 104 dtcer104 8 8 2 iclk 0008 7169h icu dtc transfer reques t enable register 105 dtcer105 8 8 2 iclk 0008 716ah icu dtc transfer reques t enable register 106 dtcer106 8 8 2 iclk 0008 716bh icu dtc transfer reques t enable register 107 dtcer107 8 8 2 iclk 0008 716ch icu dtc transfer reques t enable register 108 dtcer108 8 8 2 iclk 0008 716dh icu dtc transfer reques t enable register 109 dtcer109 8 8 2 iclk 0008 716eh icu dtc transfer reques t enable register 110 dtcer110 8 8 2 iclk 0008 716fh icu dtc transfer reques t enable register 111 dtcer111 8 8 2 iclk 0008 7170h icu dtc transfer reques t enable register 112 dtcer112 8 8 2 iclk 0008 7171h icu dtc transfer reques t enable register 113 dtcer113 8 8 2 iclk 0008 7172h icu dtc transfer reques t enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc transfer reques t enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc transfer reques t enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc transfer reques t enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc transfer reques t enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc transfer reques t enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc transfer reques t enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc transfer reques t enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc transfer reques t enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc transfer reques t enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc transfer reques t enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc transfer reques t enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc transfer reques t enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc transfer reques t enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc transfer reques t enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc transfer reques t enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc transfer reques t enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc transfer reques t enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc transfer reques t enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc transfer reques t enable register 141 dtcer141 8 8 2 iclk 0008 718eh icu dtc transfer reques t enable register 142 dtcer142 8 8 2 iclk 0008 718fh icu dtc transfer reques t enable register 143 dtcer143 8 8 2 iclk 000 8 7190h icu dtc transfer reques t enable register 144 dtcer144 8 8 2 iclk 0008 7191h icu dtc transfer reques t enable register 145 dtcer145 8 8 2 iclk 0008 7195h icu dtc transfer reques t enable register 149 dtcer149 8 8 2 iclk 0008 7196h icu dtc transfer reques t enable register 150 dtcer150 8 8 2 iclk 0008 7197h icu dtc transfer reques t enable register 151 dtcer151 8 8 2 iclk 0008 7198h icu dtc transfer reques t enable register 152 dtcer152 8 8 2 iclk 0008 7199h icu dtc transfer reques t enable register 153 dtcer153 8 8 2 iclk 0008 719fh icu dtc transfer reques t enable register 159 dtcer159 8 8 2 iclk 0008 71a0h icu dtc transfer reques t enable register 160 dtcer160 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (6/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 40 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 71a1h icu dtc transfer reques t enable register 161 dtcer161 8 8 2 iclk 0008 71a2h icu dtc transfer reques t enable register 162 dtcer162 8 8 2 iclk 0008 71adh icu dtc transfer reques t enable register 173 dtcer173 8 8 2 iclk 0008 71aeh icu dtc transfer reques t enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc transfer reques t enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc transfer reques t enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc transfer reques t enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc transfer reques t enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc transfer reques t enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc transfer reques t enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc transfer reques t enable register 184 dtcer184 8 8 2 iclk 0008 71bah icu dtc transfer reques t enable register 186 dtcer186 8 8 2 iclk 0008 71bbh icu dtc transfer reques t enable register 187 dtcer187 8 8 2 iclk 0008 71bdh icu dtc transfer reques t enable register 189 dtcer189 8 8 2 iclk 0008 71beh icu dtc transfer reques t enable register 190 dtcer190 8 8 2 iclk 0008 71c0h icu dtc transfer reques t enable register 192 dtcer192 8 8 2 iclk 0008 71c1h icu dtc transfer reques t enable register 193 dtcer193 8 8 2 iclk 0008 71c3h icu dtc transfer reques t enable register 195 dtcer195 8 8 2 iclk 0008 71c4h icu dtc transfer reques t enable register 196 dtcer196 8 8 2 iclk 0008 71cbh icu dtc transfer request enable register 203* 2 dtcer203 8 8 2 iclk 0008 71cch icu dtc transfer request enable register 204* 2 dtcer204 8 8 2 iclk 0008 71cdh icu dtc transfer request enable register 205* 2 dtcer205 8 8 2 iclk 0008 71ceh icu dtc transfer request enable register 206* 2 dtcer206 8 8 2 iclk 0008 71cfh icu dtc transfer request enable register 207* 2 dtcer207 8 8 2 iclk 0008 71d0h icu dtc transfer request enable register 208* 2 dtcer208 8 8 2 iclk 0008 71d1h icu dtc transfer request enable register 209* 2 dtcer209 8 8 2 iclk 0008 71d2h icu dtc transfer request enable register 210* 2 dtcer210 8 8 2 iclk 0008 71d4h icu dtc transfer request enable register 212* 2 dtcer212 8 8 2 iclk 0008 71d5h icu dtc transfer request enable register 213* 2 dtcer213 8 8 2 iclk 0008 71d6h icu dtc transfer request enable register 214* 2 dtcer214 8 8 2 iclk 0008 71d7h icu dtc transfer request enable register 215* 2 dtcer215 8 8 2 iclk 0008 71d8h icu dtc transfer request enable register 216* 2 dtcer216 8 8 2 iclk 0008 71d9h icu dtc transfer request enable register 217* 2 dtcer217 8 8 2 iclk 0008 71dbh icu dtc transfer reques t enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc transfer request enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc transfer reques t enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc transfer reques t enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc transfer reques t enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc transfer reques t enable register 228 dtcer228 8 8 2 iclk 0008 71eeh icu dtc transfer request enable register 238* 2 dtcer238 8 8 2 iclk 0008 71efh icu dtc transfer request enable register 239* 2 dtcer239 8 8 2 iclk 0008 71f1h icu dtc transfer request enable register 241* 2 dtcer241 8 8 2 iclk 0008 71f2h icu dtc transfer request enable register 242* 2 dtcer242 8 8 2 iclk 0008 71f3h icu dtc transfer request enable register 243* 2 dtcer243 8 8 2 iclk 0008 71f4h icu dtc transfer request enable register 244* 2 dtcer244 8 8 2 iclk 0008 71f7h icu dtc transfer reques t enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc transfer reques t enable register 248 dtcer248 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7206h icu interrupt request enable register 06* 2 ier06 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (7/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 41 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19* 2 ier19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a* 2 ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d* 2 ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt generation register swintr 8 8 2 ic lk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 ic lk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 ic lk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 ic lk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 ic lk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 ic lk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 ic lk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 ic lk 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 ic lk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 ic lk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 ic lk 0008 7328h icu interrupt source priority register 040* 2 ipr040 8 8 2 iclk 0008 7329h icu interrupt source priority register 041* 2 ipr041 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 ic lk 0008 7330h icu interrupt source priority register 048* 2 ipr048 8 8 2 iclk 0008 7331h icu interrupt source priority register 049* 2 ipr049 8 8 2 iclk 0008 7332h icu interrupt source priority register 050* 2 ipr050 8 8 2 iclk 0008 7333h icu interrupt source priority register 051* 2 ipr051 8 8 2 iclk 0008 7334h icu interrupt source priority register 052* 2 ipr052 8 8 2 iclk 0008 7335h icu interrupt source priority register 053* 2 ipr053 8 8 2 iclk 0008 7336h icu interrupt source priority register 054* 2 ipr054 8 8 2 iclk 0008 7337h icu interrupt source priority register 055* 2 ipr055 8 8 2 iclk 0008 7338h icu interrupt source priority register 056* 2 ipr056 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 ic lk 0008 733bh icu interrupt source priority register 059* 2 ipr059 8 8 2 iclk 0008 733ch icu interrupt source priority register 060* 2 ipr060 8 8 2 iclk 0008 733dh icu interrupt source priority register 061* 2 ipr061 8 8 2 iclk 0008 733eh icu interrupt source priority register 062* 2 ipr062 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (8/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 42 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 733fh icu interrupt source priority register 063* 2 ipr063 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 ic lk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 ic lk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 ic lk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 ic lk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 ic lk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 ic lk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 ic lk 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 ic lk 0008 7358h icu interrupt source priority register 088 ipr088 8 8 2 ic lk 0008 7359h icu interrupt source priority register 089 ipr089 8 8 2 ic lk 0008 7362h icu interrupt source priority register 098* 2 ipr098 8 8 2 iclk 0008 7363h icu interrupt source priority register 099* 2 ipr099 8 8 2 iclk 0008 7364h icu interrupt source priority register 100* 2 ipr100 8 8 2 iclk 0008 7365h icu interrupt source priority register 101* 2 ipr101 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 ic lk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 ic lk 0008 7368h icu interrupt source priority register 104 ipr104 8 8 2 ic lk 0008 7369h icu interrupt source priority register 105 ipr105 8 8 2 ic lk 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 ic lk 0008 736bh icu interrupt source priority register 107 ipr107 8 8 2 ic lk 0008 736ch icu interrupt source priority register 108 ipr108 8 8 2 ic lk 0008 736dh icu interrupt source priority register 109 ipr109 8 8 2 ic lk 0008 736eh icu interrupt source priority register 110 ipr110 8 8 2 ic lk 0008 736fh icu interrupt source priority register 111 ipr111 8 8 2 ic lk 0008 7370h icu interrupt source priority register 112 ipr112 8 8 2 ic lk 0008 7371h icu interrupt source priority register 113 ipr113 8 8 2 ic lk 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 ic lk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 ic lk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 ic lk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 ic lk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 ic lk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 ic lk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 ic lk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 ic lk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 ic lk 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 ic lk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 ic lk 0008 738eh icu interrupt source priority register 142 ipr142 8 8 2 ic lk 0008 7392h icu interrupt source priority register 146 ipr146 8 8 2 ic lk 0008 7395h icu interrupt source priority register 149 ipr149 8 8 2 ic lk 0008 7397h icu interrupt source priority register 151 ipr151 8 8 2 ic lk 0008 7399h icu interrupt source priority register 153 ipr153 8 8 2 ic lk 0008 739fh icu interrupt source priority register 159 ipr159 8 8 2 ic lk 0008 73a3h icu interrupt source priority register 163 ipr163 8 8 2 ic lk 0008 73a8h icu interrupt source priority register 168 ipr168 8 8 2 ic lk 0008 73adh icu interrupt source priority register 173 ipr173 8 8 2 ic lk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 ic lk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 ic lk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 ic lk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 ic lk 0008 73bah icu interrupt source priority register 186 ipr186 8 8 2 ic lk table 4.1 list of i/o regist ers (address order) (9/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 43 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 73bdh icu interrupt source priority register 189 ipr189 8 8 2 ic lk 0008 73c0h icu interrupt source priority register 192 ipr192 8 8 2 ic lk 0008 73c3h icu interrupt source priority register 195 ipr195 8 8 2 ic lk 0008 73cah icu interrupt source priority register 202* 2 ipr202 8 8 2 iclk 0008 73cbh icu interrupt source priority register 203* 2 ipr203 8 8 2 iclk 0008 73cch icu interrupt source priority register 204* 2 ipr204 8 8 2 iclk 0008 73cdh icu interrupt source priority register 205* 2 ipr205 8 8 2 iclk 0008 73ceh icu interrupt source priority register 206* 2 ipr206 8 8 2 iclk 0008 73cfh icu interrupt source priority register 207* 2 ipr207 8 8 2 iclk 0008 73d0h icu interrupt source priority register 208* 2 ipr208 8 8 2 iclk 0008 73d1h icu interrupt source priority register 209* 2 ipr209 8 8 2 iclk 0008 73d2h icu interrupt source priority register 210* 2 ipr210 8 8 2 iclk 0008 73d3h icu interrupt source priority register 211* 2 ipr211 8 8 2 iclk 0008 73d4h icu interrupt source priority register 212* 2 ipr212 8 8 2 iclk 0008 73d5h icu interrupt source priority register 213* 2 ipr213 8 8 2 iclk 0008 73d6h icu interrupt source priority register 214* 2 ipr214 8 8 2 iclk 0008 73d7h icu interrupt source priority register 215* 2 ipr215 8 8 2 iclk 0008 73d8h icu interrupt source priority register 216* 2 ipr216 8 8 2 iclk 0008 73d9h icu interrupt source priority register 217* 2 ipr217 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 ic lk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 ic lk 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 ic lk 0008 73eeh icu interrupt source priority register 238* 2 ipr238 8 8 2 iclk 0008 73efh icu interrupt source priority register 239* 2 ipr239 8 8 2 iclk 0008 73f0h icu interrupt source priority register 240* 2 ipr240 8 8 2 iclk 0008 73f1h icu interrupt source priority register 241* 2 ipr241 8 8 2 iclk 0008 73f2h icu interrupt source priority register 242* 2 ipr242 8 8 2 iclk 0008 73f3h icu interrupt source priority register 243* 2 ipr243 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244* 2 ipr244 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 ic lk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 ic lk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 ic lk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 ic lk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 1 61 6 2 i c l k 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 icl k 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 icl k 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 or 3 pclkb 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8004h cmt0 compare match counter cmcnt 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (10/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 44 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 8006h cmt0 compare match constant register cmcor 16 16 2 or 3 pc lkb 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 800ah cmt1 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 800ch cmt1 compare match constant register cmcor 16 16 2 or 3 pc lkb 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2 or 3 pclkb 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8014h cmt2 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 8016h cmt2 compare match constant register cmcor 16 16 2 or 3 pc lkb 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 801ah cmt3 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 801ch cmt3 compare match constant register cmcor 16 16 2 or 3 pc lkb 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 or 3 pclkb 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 or 3 pclkb 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 or 3 pclkb 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2 or 3 pclkb 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2 or 3 pclkb 0008 80c0h da d/a data register 0 dadr0 16 16 2 or 3 pclkb 0008 80c2h da d/a data register 1* 2 dadr1 16 16 2 or 3 pclkb 0008 80c4h da d/a control register dacr 8 8 2 or 3 pclkb 0008 80c5h da dadrm format select register dadpr 8 8 2 or 3 pclkb 0008 80c6h da d/a a/d synchronous start control register* 2 daadscr 8 8 2 or 3 pclkb 0008 8200h tmr0 timer control register tcr 8 8 2 or 3 pclkb 0008 8201h tmr1 timer control register tcr 8 8 2 or 3 pclkb 0008 8202h tmr0 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8203h tmr1 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8204h tmr0 time constant register a tcora 8 8 2 or 3 pclkb 0008 8205h tmr1 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8206h tmr0 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8208h tmr0 timer counter tcnt 8 8 2 or 3 pclkb 0008 8209h tmr1 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 820ah tmr0 timer counter control register tccr 8 8 2 or 3 pclkb 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 8210h tmr2 timer control register tcr 8 8 2 or 3 pclkb 0008 8211h tmr3 timer control register tcr 8 8 2 or 3 pclkb 0008 8212h tmr2 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8213h tmr3 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8214h tmr2 time constant register a tcora 8 8 2 or 3 pclkb 0008 8215h tmr3 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8216h tmr2 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8218h tmr2 timer counter tcnt 8 8 2 or 3 pclkb 0008 8219h tmr3 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 821ah tmr2 timer counter control register tccr 8 8 2 or 3 pclkb 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 8220h tmr4 timer control register tcr 8 8 2 or 3 pclkb 0008 8221h tmr5 timer control register tcr 8 8 2 or 3 pclkb 0008 8222h tmr4 timer control / status register tcsr 8 8 2 or 3 pclkb 0008 8223h tmr5 timer control / status register tcsr 8 8 2 or 3 pclkb 0008 8224h tmr4 time constant register a tcora 8 8 2 or 3 pclkb 0008 8225h tmr5 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8226h tmr4 time constant register b tcorb 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (11/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 45 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 8227h tmr5 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8228h tmr4 timer counter tcnt 8 8 2 or 3 pclkb 0008 8229h tmr5 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 822ah tmr4 timer counter control register tccr 8 8 2 or 3 pclkb 0008 822bh tmr5 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 8230h tmr6 timer control register tcr 8 8 2 or 3 pclkb 0008 8231h tmr7 timer control register tcr 8 8 2 or 3 pclkb 0008 8232h tmr6 timer control / status register tcsr 8 8 2 or 3 pclkb 0008 8233h tmr7 timer control / status register tcsr 8 8 2 or 3 pclkb 0008 8234h tmr6 time constant register a tcora 8 8 2 or 3 pclkb 0008 8235h tmr7 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8236h tmr6 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8237h tmr7 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8238h tmr6 timer counter tcnt 8 8 2 or 3 pclkb 0008 8239h tmr7 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 823ah tmr6 timer counter control register tccr 8 8 2 or 3 pclkb 0008 823bh tmr7 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 8280h crc crc control register crccr 8 8 2 or 3 pclkb 0008 8281h crc crc data input register crcdir 8 8 2 or 3 pclkb 0008 8282h crc crc data output register crcdor 16 16 2 or 3 pclkb 0008 8300h riic0 i 2 c-bus control register 1 iccr1 8 8 2 or 3 pclkb 0008 8301h riic0 i 2 c-bus control register 2 iccr2 8 8 2 or 3 pclkb 0008 8302h riic0 i 2 c-bus mode register 1 icmr1 8 8 2 or 3 pclkb 0008 8303h riic0 i 2 c-bus mode register 2 icmr2 8 8 2 or 3 pclkb 0008 8304h riic0 i 2 c-bus mode register 3 icmr3 8 8 2 or 3 pclkb 0008 8305h riic0 i 2 c-bus function enable register icfer 8 8 2 or 3 pclkb 0008 8306h riic0 i 2 c-bus status enable register icser 8 8 2 or 3 pclkb 0008 8307h riic0 i 2 c-bus interrupt enable register icier 8 8 2 or 3 pclkb 0008 8308h riic0 i 2 c-bus status register 1 icsr1 8 8 2 or 3 pclkb 0008 8309h riic0 i 2 c-bus status register 2 icsr2 8 8 2 or 3 pclkb 0008 830ah riic0 slave address register l0 sarl0 8 8 2 or 3 pclkb 0008 830bh riic0 slave address register u0 saru0 8 8 2 or 3 pclkb 0008 830ch riic0 slave address register l1 sarl1 8 8 2 or 3 pclkb 0008 830dh riic0 slave address register u1 saru1 8 8 2 or 3 pclkb 0008 830eh riic0 slave address register l2 sarl2 8 8 2 or 3 pclkb 0008 830fh riic0 slave address register u2 saru2 8 8 2 or 3 pclkb 0008 8310h riic0 i 2 c-bus bit rate low-level register icbrl 8 8 2 or 3 pclkb 0008 8311h riic0 i 2 c-bus bit rate high-level register icbrh 8 8 2 or 3 pclkb 0008 8312h riic0 i 2 c-bus transmit data register icdrt 8 8 2 or 3 pclkb 0008 8313h riic0 i 2 c-bus receive data register icdrr 8 8 2 or 3 pclkb 0008 8380h rspi0 rspi control register spcr 8 8 2 or 3 pclkb 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 or 3 pclkb 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 or 3 pclkb 0008 8383h rspi0 rspi status register spsr 8 8 2 or 3 pclkb 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 or 3 pclkb 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 or 3 pclk b 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 or 3 pclkb 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 or 3 pclkb 0008 838bh rspi0 rspi data control register spdcr 8 8 2 or 3 pclkb 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 or 3 pclkb 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 or 3 pclkb 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 or 3 pclk b table 4.1 list of i/o register s (address order) (12/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 46 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 or 3 pclkb 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 or 3 pclkb 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 or 3 pclkb 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 or 3 pclkb 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 or 3 pclkb 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 or 3 pclkb 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 or 3 pclkb 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 or 3 pclkb 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 or 3 pclkb 0008 9000h s12ad a/d control register adcsr 16 16 2 or 3 pclkb 0008 9004h s12ad a/d channel select register a0 adansa0 16 16 2 or 3 pclkb 0008 9006h s12ad a/d channel select register a1 adansa1 16 16 2 or 3 pclkb 0008 9008h s12ad a/d-converted value addition/average function ch annel select register 0 adads0 16 16 2 or 3 pclkb 0008 900ah s12ad a/d-converted value addition/average function ch annel select register 1 adads1 16 16 2 or 3 pclkb 0008 900ch s12ad a/d-converted value addition/average count selec t register adadc 8 8 2 or 3 pclkb 0008 900eh s12ad a/d control extended register adcer 16 16 2 or 3 pcl kb 0008 9010h s12ad a/d conversion start trigger select register adst rgr 16 16 2 or 3 pclkb 0008 9014h s12ad a/d channel select register b0 adansb0 16 16 2 or 3 pclkb 0008 9016h s12ad a/d channel select register b1 adansb1 16 16 2 or 3 pclkb 0008 9018h s12ad a/d data duplication register addbldr 16 16 2 or 3 p clkb 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2 or 3 p clkb 0008 9020h s12ad a/d data register 0 addr0 16 16 2 or 3 pclkb 0008 9022h s12ad a/d data register 1 addr1 16 16 2 or 3 pclkb 0008 9024h s12ad a/d data register 2 addr2 16 16 2 or 3 pclkb 0008 9026h s12ad a/d data register 3 addr3 16 16 2 or 3 pclkb 0008 9040h s12ad a/d data regis ter 16 addr16 16 16 2 or 3 pclkb 0008 907ah s12ad a/d disconnection detection control register addi scr 8 8 2 or 3 pclkb 0008 9080h s12ad a/d group scan priority control register adgspcr 1 61 6 2 o r 3 p c l k b 0008 9084h s12ad a/d data duplication register a addbldra 16 16 2 or 3 pclkb 0008 9086h s12ad a/d data duplication register b addbldrb 16 16 2 or 3 pclkb 0008 90d4h s12ad a/d channel selec t register c0 adansc0 16 16 2 or 3 pclkb 0008 90d6h s12ad a/d channel selec t register c1 adansc1 16 16 2 or 3 pclkb 0008 90d9h s12ad a/d group c trigger select register adgctrgr 8 8 2 o r 3 pclkb 0008 90ddh s12ad a/d sampling state register l adsstrl 8 8 2 or 3 pcl kb 0008 90e0h s12ad a/d sampling state register 0 adsstr0 8 8 2 or 3 pcl kb 0008 90e1h s12ad a/d sampling state register 1 adsstr1 8 8 2 or 3 pcl kb 0008 90e2h s12ad a/d sampling state register 2 adsstr2 8 8 2 or 3 pcl kb 0008 90e3h s12ad a/d sampling state register 3 adsstr3 8 8 2 or 3 pcl kb 0008 91a0h s12ad a/d programmable gain amplifier control register adpgacr 16 16 2 or 3 pclkb 0008 91a2h s12ad a/d programmable gain amplifier gain setting reg ister 0 adpgags0 16 16 2 or 3 pclkb 0008 9200h s12ad1 a/d control register adcsr 16 16 2 or 3 pclkb 0008 9204h s12ad1 a/d channel select register a0 adansa0 16 16 2 or 3 pclkb 0008 9206h s12ad1 a/d channel select register a1 adansa1 16 16 2 or 3 pclkb 0008 9208h s12ad1 a/d-converted value addition/average function c hannel select register 0 adads0 16 16 2 or 3 pclkb 0008 920ah s12ad1 a/d-converted value addition/average function c hannel select register 1 adads1 16 16 2 or 3 pclkb 0008 920ch s12ad1 a/d-converted value addition/average count sele ct register adadc 8 8 2 or 3 pclkb 0008 920eh s12ad1 a/d control extended register adcer 16 16 2 or 3 pc lkb 0008 9210h s12ad1 a/d conversion start trigger select register ads trgr 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (13/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 47 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 9214h s12ad1 a/d channel select register b0 adansb0 16 16 2 or 3 pclkb 0008 9216h s12ad1 a/d channel select register b1 adansb1 16 16 2 or 3 pclkb 0008 9218h s12ad1 a/d data duplication register addbldr 16 16 2 or 3 pclkb 0008 921eh s12ad1 a/d self-diagnosis data register adrd 16 16 2 or 3 pclkb 0008 9220h s12ad1 a/d data register 0 addr0 16 16 2 or 3 pclkb 0008 9222h s12ad1 a/d data register 1 addr1 16 16 2 or 3 pclkb 0008 9224h s12ad1 a/d data register 2 addr2 16 16 2 or 3 pclkb 0008 9226h s12ad1 a/d data register 3 addr3 16 16 2 or 3 pclkb 0008 9240h s12ad1 a/d data register 16 addr16 16 16 2 or 3 pclkb 0008 9266h s12ad1 a/d sample-and-hold circuit control register ads hcr 16 16 2 or 3 pclkb 0008 927ah s12ad1 a/d disconnection detection control register add iscr 8 8 2 or 3 pclkb 0008 9280h s12ad1 a/d group scan priority control register adgspcr 16 16 2 or 3 pclkb 0008 9284h s12ad1 a/d data duplication register a addbldra 16 16 2 or 3 pclkb 0008 9286h s12ad1 a/d data duplication register b addbldrb 16 16 2 or 3 pclkb 0008 92d4h s12ad1 a/d channel select register c0 adansc0 16 16 2 or 3 pclkb 0008 92d6h s12ad1 a/d channel select register c1 adansc1 16 16 2 or 3 pclkb 0008 92d9h s12ad1 a/d group c trigger select register adgctrgr 8 8 2 or 3 pclkb 0008 92ddh s12ad1 a/d sampling state register l adsstrl 8 8 2 or 3 pc lkb 0008 92e0h s12ad1 a/d sampling state register 0 adsstr0 8 8 2 or 3 pc lkb 0008 92e1h s12ad1 a/d sampling state register 1 adsstr1 8 8 2 or 3 pc lkb 0008 92e2h s12ad1 a/d sampling state register 2 adsstr2 8 8 2 or 3 pc lkb 0008 92e3h s12ad1 a/d sampling state register 3 adsstr3 8 8 2 or 3 pc lkb 0008 93a0h s12ad1 a/d programmable gain amplifier control register adpgacr 16 16 2 or 3 pclkb 0008 93a2h s12ad1 a/d programmable gain amplifier gain setting re gister 0 adpgags0 16 16 2 or 3 pclkb 0008 9400h s12ad2 a/d control register adcsr 16 16 2 or 3 pclkb 0008 9404h s12ad2 a/d channel select register a0 adansa0 16 16 2 or 3 pclkb 0008 9408h s12ad2 a/d-converted value addition/average function c hannel select register 0 adads0 16 16 2 or 3 pclkb 0008 940ch s12ad2 a/d-converted value addition/average count sele ct register adadc 8 8 2 or 3 pclkb 0008 940eh s12ad2 a/d control extended register adcer 16 16 2 or 3 pc lkb 0008 9410h s12ad2 a/d conversion start trigger select register ads trgr 16 16 2 or 3 pclkb 0008 9412h s12ad2 a/d conversion extended input control register a dexicr 16 16 2 or 3 pclkb 0008 9414h s12ad2 a/d channel select register b0 adansb0 16 16 2 or 3 pclkb 0008 9418h s12ad2 a/d data duplication register addbldr 16 16 2 or 3 pclkb 0008 941ch s12ad2 a/d internal reference voltage data register ado cdr 16 16 2 or 3 pclkb 0008 941eh s12ad2 a/d self-diagnosis data register adrd 16 16 2 or 3 pclkb 0008 9420h s12ad2 a/d data register 0 addr0 16 16 2 or 3 pclkb 0008 9422h s12ad2 a/d data register 1 addr1 16 16 2 or 3 pclkb 0008 9424h s12ad2 a/d data register 2 addr2 16 16 2 or 3 pclkb 0008 9426h s12ad2 a/d data register 3 addr3 16 16 2 or 3 pclkb 0008 9428h s12ad2 a/d data register 4 addr4 16 16 2 or 3 pclkb 0008 942ah s12ad2 a/d data register 5 addr5 16 16 2 or 3 pclkb 0008 942ch s12ad2 a/d data register 6 addr6 16 16 2 or 3 pclkb 0008 942eh s12ad2 a/d data register 7 addr7 16 16 2 or 3 pclkb 0008 9430h s12ad2 a/d data register 8 addr8 16 16 2 or 3 pclkb 0008 9432h s12ad2 a/d data register 9 addr9 16 16 2 or 3 pclkb 0008 9434h s12ad2 a/d data register 10 addr10 16 16 2 or 3 pclkb 0008 9436h s12ad2 a/d data register 11 addr11 16 16 2 or 3 pclkb 0008 947ah s12ad2 a/d disconnection detection control register add iscr 8 8 2 or 3 pclkb 0008 9480h s12ad2 a/d group scan priority control register adgspcr 16 16 2 or 3 pclkb 0008 9484h s12ad2 a/d data duplication register a addbldra 16 16 2 or 3 pclkb 0008 9486h s12ad2 a/d data duplication register b addbldrb 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (14/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 48 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 94d4h s12ad2 a/d channel select register c0 adansc0 16 16 2 or 3 pclkb 0008 94d9h s12ad2 a/d group c trigger select register adgctrgr 8 8 2 or 3 pclkb 0008 94dfh s12ad2 a/d sampling state register o adsstro 8 8 2 or 3 pc lkb 0008 94e0h s12ad2 a/d sampling state register 0 adsstr0 8 8 2 or 3 pc lkb 0008 94e1h s12ad2 a/d sampling state register 1 adsstr1 8 8 2 or 3 pc lkb 0008 94e2h s12ad2 a/d sampling state register 2 adsstr2 8 8 2 or 3 pc lkb 0008 94e3h s12ad2 a/d sampling state register 3 adsstr3 8 8 2 or 3 pc lkb 0008 94e4h s12ad2 a/d sampling state register 4 adsstr4 8 8 2 or 3 pc lkb 0008 94e5h s12ad2 a/d sampling state register 5 adsstr5 8 8 2 or 3 pc lkb 0008 94e6h s12ad2 a/d sampling state register 6 adsstr6 8 8 2 or 3 pc lkb 0008 94e7h s12ad2 a/d sampling state register 7 adsstr7 8 8 2 or 3 pc lkb 0008 94e8h s12ad2 a/d sampling state register 8 adsstr8 8 8 2 or 3 pc lkb 0008 94e9h s12ad2 a/d sampling state register 9 adsstr9 8 8 2 or 3 pc lkb 0008 94eah s12ad2 a/d sampling state register 10 adsstr10 8 8 2 or 3 pclkb 0008 94ebh s12ad2 a/d sampling state register 11 adsstr11 8 8 2 or 3 pclkb 0008 a020h sci1 serial mode register smr 8 8 2 or 3 pclkb 0008 a021h sci1 bit rate register brr 8 8 2 or 3 pclkb 0008 a022h sci1 serial control register scr 8 8 2 or 3 pclkb 0008 a023h sci1 transmit data register tdr 8 8 2 or 3 pclkb 0008 a024h sci1 serial status register ssr 8 8 2 or 3 pclkb 0008 a025h sci1 receive data register rdr 8 8 2 or 3 pclkb 0008 a026h smci1 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a027h sci1 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a028h sci1 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a02ch sci1 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a02dh sci1 spi mode register spmr 8 8 2 or 3 pclkb 0008 a02eh sci1 transmit data register hl tdrhl 16 16 4 or 5 pclkb 0008 a02eh sci1 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 a02fh sci1 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a030h sci1 receive data register hl rdrhl 16 16 4 or 5 pclkb 0008 a030h sci1 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a031h sci1 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a032h sci1 modulation duty register mddr 8 8 2 or 3 pclkb 0008 a0a0h sci5 serial mode register smr 8 8 2 or 3 pclkb 0008 a0a1h sci5 bit rate register brr 8 8 2 or 3 pclkb 0008 a0a2h sci5 serial control register scr 8 8 2 or 3 pclkb 0008 a0a3h sci5 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0a4h sci5 serial status register ssr 8 8 2 or 3 pclkb 0008 a0a5h sci5 receive data register rdr 8 8 2 or 3 pclkb 0008 a0a6h smci5 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0a7h sci5 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0a8h sci5 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0ach sci5 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0adh sci5 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0aeh sci5 transmit data register hl tdrhl 16 16 4 or 5 pclkb 0008 a0aeh sci5 transmit data register h tdrh 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (15/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 49 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 a0afh sci5 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a0b0h sci5 receive data register hl rdrhl 16 16 4 or 5 pclkb 0008 a0b0h sci5 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a0b1h sci5 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a0b2h sci5 modulation duty register mddr 8 8 2 or 3 pclkb 0008 a0c0h sci6 serial mode register smr 8 8 2 or 3 pclkb 0008 a0c1h sci6 bit rate register brr 8 8 2 or 3 pclkb 0008 a0c2h sci6 serial control register scr 8 8 2 or 3 pclkb 0008 a0c3h sci6 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0c4h sci6 serial status register ssr 8 8 2 or 3 pclkb 0008 a0c5h sci6 receive data register rdr 8 8 2 or 3 pclkb 0008 a0c6h smci6 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0c7h sci6 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0c8h sci6 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0cch sci6 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0cdh sci6 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0ceh sci6 transmit data register hl tdrhl 16 16 4 or 5 pclkb 0008 a0ceh sci6 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 a0cfh sci6 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a0d0h sci6 receive data register hl rdrhl 16 16 4 or 5 pclkb 0008 a0d0h sci6 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a0d1h sci6 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a0d2h sci6 modulation duty register mddr 8 8 2 or 3 pclkb 0008 b000h cac cac control register 0 cacr0 8 8 2 or 3 pclkb 0008 b001h cac cac control register 1 cacr1 8 8 2 or 3 pclkb 0008 b002h cac cac control register 2 cacr2 8 8 2 or 3 pclkb 0008 b003h cac cac interrupt request enable register caicr 8 8 2 or 3 pclkb 0008 b004h cac cac status register castr 8 8 2 or 3 pclkb 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2 or 3 pclkb 0008 b008h cac cac lower-limit value setting register callvr 16 16 2 or 3 pclkb 0008 b00ah cac cac counter buffer register cacntbr 16 16 2 or 3 pclkb 0008 b080h doc doc control register docr 8 8 2 or 3 pclkb 0008 b082h doc doc data input register dodir 16 16 2 or 3 pclkb 0008 b084h doc doc data setting register dodsr 16 16 2 or 3 pclkb 0008 c000h port0 port direction register pdr 8 8 2 or 3 pclkb 0008 c001h port1 port direction register pdr 8 8 2 or 3 pclkb 0008 c002h port2 port direction register pdr 8 8 2 or 3 pclkb 0008 c003h port3 port direction register pdr 8 8 2 or 3 pclkb 0008 c004h port4 port direction register pdr 8 8 2 or 3 pclkb 0008 c005h port5 port direction register pdr 8 8 2 or 3 pclkb 0008 c006h port6 port direction register pdr 8 8 2 or 3 pclkb 0008 c007h port7 port direction register pdr 8 8 2 or 3 pclkb 0008 c008h port8 port direction register pdr 8 8 2 or 3 pclkb 0008 c009h port9 port direction register pdr 8 8 2 or 3 pclkb 0008 c00ah porta port direction register pdr 8 8 2 or 3 pclkb 0008 c00bh portb port direction register pdr 8 8 2 or 3 pclkb 0008 c00dh portd port direction register pdr 8 8 2 or 3 pclkb 0008 c00eh porte port direction register pdr 8 8 2 or 3 pclkb 0008 c020h port0 port output data register podr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (16/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 50 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 c021h port1 port output data register podr 8 8 2 or 3 pclkb 0008 c022h port2 port output data register podr 8 8 2 or 3 pclkb 0008 c023h port3 port output data register podr 8 8 2 or 3 pclkb 0008 c024h port4 port output data register podr 8 8 2 or 3 pclkb 0008 c025h port5 port output data register podr 8 8 2 or 3 pclkb 0008 c026h port6 port output data register podr 8 8 2 or 3 pclkb 0008 c027h port7 port output data register podr 8 8 2 or 3 pclkb 0008 c028h port8 port output data register podr 8 8 2 or 3 pclkb 0008 c029h port9 port output data register podr 8 8 2 or 3 pclkb 0008 c02ah porta port output data register podr 8 8 2 or 3 pclkb 0008 c02bh portb port output data register podr 8 8 2 or 3 pclkb 0008 c02dh portd port output data register podr 8 8 2 or 3 pclkb 0008 c02eh porte port output data register podr 8 8 2 or 3 pclkb 0008 c040h port0 port input data register pidr 8 8 2 or 3 pclkb 0008 c041h port1 port input data register pidr 8 8 2 or 3 pclkb 0008 c042h port2 port input data register pidr 8 8 2 or 3 pclkb 0008 c043h port3 port input data register pidr 8 8 2 or 3 pclkb 0008 c044h port4 port input data register pidr 8 8 2 or 3 pclkb 0008 c045h port5 port input data register pidr 8 8 2 or 3 pclkb 0008 c046h port6 port input data register pidr 8 8 2 or 3 pclkb 0008 c047h port7 port input data register pidr 8 8 2 or 3 pclkb 0008 c048h port8 port input data register pidr 8 8 2 or 3 pclkb 0008 c049h port9 port input data register pidr 8 8 2 or 3 pclkb 0008 c04ah porta port input data register pidr 8 8 2 or 3 pclkb 0008 c04bh portb port input data register pidr 8 8 2 or 3 pclkb 0008 c04dh portd port input data register pidr 8 8 2 or 3 pclkb 0008 c04eh porte port input data register pidr 8 8 2 or 3 pclkb 0008 c060h port0 port mode register pmr 8 8 2 or 3 pclkb 0008 c061h port1 port mode register pmr 8 8 2 or 3 pclkb 0008 c062h port2 port mode register pmr 8 8 2 or 3 pclkb 0008 c063h port3 port mode register pmr 8 8 2 or 3 pclkb 0008 c067h port7 port mode register pmr 8 8 2 or 3 pclkb 0008 c068h port8 port mode register pmr 8 8 2 or 3 pclkb 0008 c069h port9 port mode register pmr 8 8 2 or 3 pclkb 0008 c06ah porta port mode register pmr 8 8 2 or 3 pclkb 0008 c06bh portb port mode register pmr 8 8 2 or 3 pclkb 0008 c06dh portd port mode register pmr 8 8 2 or 3 pclkb 0008 c06eh porte port mode register pmr 8 8 2 or 3 pclkb 0008 c080h port0 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c08eh port7 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c08fh port7 open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb 0008 c090h port8 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c092h port9 open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c093h port9 open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb 0008 c094h porta open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c095h porta open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb 0008 c096h portb open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c097h portb open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb table 4.1 list of i/o register s (address order) (17/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 51 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 c09ah portd open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c09bh portd open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2 or 3 pc lkb 0008 c09dh porte open drain control register 1 odr1 8 8, 16 2 or 3 pc lkb 0008 c0c0h port0 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c1h port1 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c2h port2 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c3h port3 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c4h port4 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c5h port5 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c6h port6 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c7h port7 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c8h port8 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c9h port9 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cah porta pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cbh portb pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cdh portd pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0ceh porte pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0e0h port0 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0e1h port1 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0e2h port2 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0e3h port3 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0e7h port7 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0e8h port8 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0e9h port9 drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0eah porta drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0ebh portb drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c0edh portd drive capacity con trol register dscr 8 8 2 or 3 pclk b 0008 c0eeh porte drive capacity control register dscr 8 8 2 or 3 pclk b 0008 c11fh mpc write-protect register pwpr 8 8 2 or 3 pclkb 0008 c140h mpc p00 pin function control register p00pfs 8 8 2 or 3 pc lkb 0008 c141h mpc p01 pin function control register p01pfs 8 8 2 or 3 pc lkb 0008 c142h mpc p02 pin function control register p02pfs 8 8 2 or 3 pc lkb 0008 c148h mpc p10 pin function control register p10pfs 8 8 2 or 3 pc lkb 0008 c149h mpc p11 pin function control register p11pfs 8 8 2 or 3 pc lkb 0008 c150h mpc p20 pin function control register p20pfs 8 8 2 or 3 pc lkb 0008 c151h mpc p21 pin function control register p21pfs 8 8 2 or 3 pc lkb 0008 c152h mpc p22 pin function control register p22pfs 8 8 2 or 3 pc lkb 0008 c153h mpc p23 pin function control register p23pfs 8 8 2 or 3 pc lkb 0008 c154h mpc p24 pin function control register p24pfs 8 8 2 or 3 pc lkb 0008 c158h mpc p30 pin function control register p30pfs 8 8 2 or 3 pc lkb 0008 c159h mpc p31 pin function control register p31pfs 8 8 2 or 3 pc lkb 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2 or 3 pc lkb 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2 or 3 pc lkb 0008 c160h mpc p40 pin function control register p40pfs 8 8 2 or 3 pc lkb 0008 c161h mpc p41 pin function control register p41pfs 8 8 2 or 3 pc lkb 0008 c162h mpc p42 pin function control register p42pfs 8 8 2 or 3 pc lkb 0008 c163h mpc p43 pin function control register p43pfs 8 8 2 or 3 pc lkb 0008 c164h mpc p44 pin function control register p44pfs 8 8 2 or 3 pc lkb 0008 c165h mpc p45 pin function control register p45pfs 8 8 2 or 3 pc lkb 0008 c166h mpc p46 pin function control register p46pfs 8 8 2 or 3 pc lkb 0008 c167h mpc p47 pin function control register p47pfs 8 8 2 or 3 pc lkb table 4.1 list of i/o register s (address order) (18/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 52 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 c168h mpc p50 pin function control register p50pfs 8 8 2 or 3 pc lkb 0008 c169h mpc p51 pin function control register p51pfs 8 8 2 or 3 pc lkb 0008 c16ah mpc p52 pin function control register p52pfs 8 8 2 or 3 pc lkb 0008 c16bh mpc p53 pin function control register p53pfs 8 8 2 or 3 pc lkb 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2 or 3 pc lkb 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2 or 3 pc lkb 0008 c170h mpc p60 pin function control register p60pfs 8 8 2 or 3 pc lkb 0008 c171h mpc p61 pin function control register p61pfs 8 8 2 or 3 pc lkb 0008 c172h mpc p62 pin function control register p62pfs 8 8 2 or 3 pc lkb 0008 c173h mpc p63 pin function control register p63pfs 8 8 2 or 3 pc lkb 0008 c174h mpc p64 pin function control register p64pfs 8 8 2 or 3 pc lkb 0008 c175h mpc p65 pin function control register p65pfs 8 8 2 or 3 pc lkb 0008 c178h mpc p70 pin function control register p70pfs 8 8 2 or 3 pc lkb 0008 c179h mpc p71 pin function control register p71pfs 8 8 2 or 3 pc lkb 0008 c17ah mpc p72 pin function control register p72pfs 8 8 2 or 3 pc lkb 0008 c17bh mpc p73 pin function control register p73pfs 8 8 2 or 3 pc lkb 0008 c17ch mpc p74 pin function control register p74pfs 8 8 2 or 3 pc lkb 0008 c17dh mpc p75 pin function control register p75pfs 8 8 2 or 3 pc lkb 0008 c17eh mpc p76 pin function control register p76pfs 8 8 2 or 3 pc lkb 0008 c180h mpc p80 pin function control register p80pfs 8 8 2 or 3 pc lkb 0008 c181h mpc p81 pin function control register p81pfs 8 8 2 or 3 pc lkb 0008 c182h mpc p82 pin function control register p82pfs 8 8 2 or 3 pc lkb 0008 c188h mpc p90 pin function control register p90pfs 8 8 2 or 3 pc lkb 0008 c189h mpc p91 pin function control register p91pfs 8 8 2 or 3 pc lkb 0008 c18ah mpc p92 pin function control register p92pfs 8 8 2 or 3 pc lkb 0008 c18bh mpc p93 pin function control register p93pfs 8 8 2 or 3 pc lkb 0008 c18ch mpc p94 pin function control register p94pfs 8 8 2 or 3 pc lkb 0008 c18dh mpc p95 pin function control register p95pfs 8 8 2 or 3 pc lkb 0008 c18eh mpc p96 pin function control register p96pfs 8 8 2 or 3 pc lkb 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2 or 3 pc lkb 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2 or 3 pc lkb 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2 or 3 pc lkb 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2 or 3 pc lkb 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2 or 3 pc lkb 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2 or 3 pc lkb 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2 or 3 pc lkb 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2 or 3 pc lkb 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2 or 3 pc lkb 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2 or 3 pc lkb 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2 or 3 pc lkb 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2 or 3 pc lkb 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2 or 3 pc lkb 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2 or 3 pc lkb 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2 or 3 pc lkb 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2 or 3 pc lkb 0008 c1aah mpc pd2 pin function cont rol register pd2pfs 8 8 2 or 3 pc lkb 0008 c1abh mpc pd3 pin function cont rol register pd3pfs 8 8 2 or 3 pc lkb 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2 or 3 pc lkb 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2 or 3 pc lkb 0008 c1aeh mpc pd6 pin function cont rol register pd6pfs 8 8 2 or 3 pc lkb 000 8 c1afh mpc pd7 pin function control register pd7pfs 8 8 2 or 3 pc lkb 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2 or 3 pc lkb table 4.1 list of i/o register s (address order) (19/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 53 of 133 apr 14, 2017 rx24t group 4. i/o registers 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2 or 3 pc lkb 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2 or 3 pc lkb 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2 or 3 pc lkb 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2 or 3 pc lkb 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2 or 3 pc lkb 0008 c290h system reset status register 0 rstsr0 8 8 4 or 5 pclkb 0008 c291h system reset status register 1 rstsr1 8 8 4 or 5 pclkb 0008 c293h system main clock oscillator forced oscillation contro l register mofcr 8 8 4 or 5 pclkb 0008 c297h system voltage monitoring circuit control register lvcm pcr 8 8 4 or 5 pclkb 0008 c298h system voltage detection level select register lvdlvlr 8 84 o r 5 p c l k b 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4 or 5 pclkb 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4 or 5 pclkb 0008 c4c0h poe input level control/status register 1 icsr1 16 8, 16 2 or 3 pclkb 0008 c4c2h poe output level control/status register 1 ocsr1 16 8, 16 2 or 3 pclkb 0008 c4c4h poe input level control/status register 2 icsr2 16 8, 16 2 or 3 pclkb 0008 c4c6h poe output level control/status register 2 ocsr2 16 8, 16 2 or 3 pclkb 0008 c4c8h poe input level control/status register 3 icsr3 16 8, 16 2 or 3 pclkb 0008 c4cah poe software port output enable register spoer 8 8 2 or 3 pclkb 0008 c4cbh poe port output enable control register 1 poecr1 8 8 2 or 3 pclkb 0008 c4cch poe port output enable control register 2 poecr2 16 16 2 o r 3 pclkb 0008 c4ceh poe port output enable control register 3* 2 poecr3 16 16 2 or 3 pclkb 0008 c4d0h poe port output enable control register 4 poecr4 16 16 2 o r 3 pclkb 0008 c4d2h poe port output enable control register 5 poecr5 16 16 2 o r 3 pclkb 0008 c4d4h poe port output enable control register 6* 2 poecr6 16 16 2 or 3 pclkb 0008 c4d6h poe input level control/status register 4 icsr4 16 8, 16 2 or 3 pclkb 0008 c4d8h poe input level control/status register 5 icsr5 16 8, 16 2 or 3 pclkb 0008 c4dah poe active level setting register 1 alr1 16 8, 16 2 or 3 p clkb 0008 c4dch poe input level control/status register 6 icsr6 16 16 2 or 3 pclkb 0008 c4deh poe active level setting register 2 alr2 16 8, 16 2 or 3 p clkb 0008 c4e0h poe input level control/status register 7 icsr7 16 8, 16 2 or 3 pclkb 0008 c4e2h poe port output enable control register 7 poecr7 16 16 2 o r 3 pclkb 0008 c4e4h poe port output enable control register 8 poecr8 16 16 2 o r 3 pclkb 0008 c4e6h poe port output enable comparator output detection fla g register poecmpfr 16 16 2 or 3 pclkb 0008 c4e8h poe port output enable comparator request select regis ter poecmpsel 16 16 2 or 3 pclkb 0008 c4f0h poe port mode mask control register 0* 2 pmmcr0 8 8 2 or 3 pclkb 0008 c4f2h poe port mode mask control register 1* 2 pmmcr1 16 16 2 or 3 pclkb 0008 c4f4h poe port mode mask control register 2* 2 pmmcr2 16 16 2 or 3 pclkb 0008 c4f6h poe port mode mask control register 3* 2 pmmcr3 16 16 2 or 3 pclkb 0008 c4f8h poe port output enable comparator request extended selection register 0* 2 poecmpex0 8 8 2 or 3 pclkb 0008 c4f9h poe port output enable comparator request extended selection register 1* 2 poecmpex1 8 8 2 or 3 pclkb 0008 c4fah poe port output enable comparator request extended selection register 2* 2 poecmpex2 8 8 2 or 3 pclkb 0008 c4fch poe port output enable comparator request extended selection register 4* 2 poecmpex4 8 8 2 or 3 pclkb 0008 c4fdh poe port output enable comparator request extended selection register 5* 2 poecmpex5 8 8 2 or 3 pclkb 000a 0c80h cmpc0 comparator control register 0 cmpctl 8 8 1 or 2 pclk b 000a 0c84h cmpc0 comparator input select register 0 cmpsel0 8 8 1 or 2 pclkb 000a 0c88h cmpc0 comparator reference voltage select register 0 cm psel1 8 8 1 or 2 pclkb 000a 0c8ch cmpc0 comparator output monitor register 0 cmpmon 8 8 1 or 2 pclkb 000a 0c90h cmpc0 comparator external output enable register 0 cmpi oc 8 8 1 or 2 pclkb table 4.1 list of i/o register s (address order) (20/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 54 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 0ca0h cmpc1 comparator control register 1 cmpctl 8 8 1 or 2 pclk b 000a 0ca4h cmpc1 comparator input select register 1 cmpsel0 8 8 1 or 2 pclkb 000a 0ca8h cmpc1 comparator reference voltage select register 1 cm psel1 8 8 1 or 2 pclkb 000a 0cach cmpc1 comparator output monitor register 1 cmpmon 8 8 1 or 2 pclkb 000a 0cb0h cmpc1 comparator external output enable register 1 cmpi oc 8 8 1 or 2 pclkb 000a 0cc0h cmpc2 comparator control register 2 cmpctl 8 8 1 or 2 pclk b 000a 0cc4h cmpc2 comparator input select register 2 cmpsel0 8 8 1 or 2 pclkb 000a 0cc8h cmpc2 comparator reference voltage select register 2 cm psel1 8 8 1 or 2 pclkb 000a 0ccch cmpc2 comparator output monitor register 2 cmpmon 8 8 1 or 2 pclkb 000a 0cd0h cmpc2 comparator external output enable register 2 cmpi oc 8 8 1 or 2 pclkb 000a 0ce0h cmpc3 comparator control register 3 cmpctl 8 8 1 or 2 pclk b 000a 0ce4h cmpc3 comparator input select register 3 cmpsel0 8 8 1 or 2 pclkb 000a 0ce8h cmpc3 comparator reference voltage select register 3 cm psel1 8 8 1 or 2 pclkb 000a 0cech cmpc3 comparator output monitor register 3 cmpmon 8 8 1 or 2 pclkb 000a 0cf0h cmpc3 comparator external output enable register 3 cmpi oc 8 8 1 or 2 pclkb 000a 8300h rscan0 bit configuration register l* 2 cfgl 16 16 2 or 3 pclkb 000a 8302h rscan0 bit configuration register h* 2 cfgh 16 16 2 or 3 pclkb 000a 8304h rscan0 control register l* 2 ctrl 16 16 2 or 3 pclkb 000a 8306h rscan0 control register h* 2 ctrh 16 16 2 or 3 pclkb 000a 8308h rscan0 status register l* 2 stsl 16 16 2 or 3 pclkb 000a 830ah rscan0 status register h* 2 stsh 16 16 2 or 3 pclkb 000a 830ch rscan0 error flag register l* 2 erfll 16 16 2 or 3 pclkb 000a 830eh rscan0 error flag register h* 2 erflh 16 16 2 or 3 pclkb 000a 8322h rscan global configuration register l* 2 gcfgl 16 16 2 or 3 pclkb 000a 8324h rscan global configuration register h* 2 gcfgh 16 16 2 or 3 pclkb 000a 8326h rscan global control register l* 2 gctrl 16 16 2 or 3 pclkb 000a 8328h rscan global control register h* 2 gctrh 16 16 2 or 3 pclkb 000a 832ah rscan global status register* 2 gsts 16 16 2 or 3 pclkb 000a 832ch rscan global error flag register* 2 gerfll 8 8 1 or 2 pclkb 000a 832eh rscan timestamp register* 2 gtsc 16 16 2 or 3 pclkb 000a 8330h rscan receive rule number configuration register* 2 gaflcfg 16 16 2 or 3 pclkb 000a 8332h rscan receive buffer number configuration register* 2 rmnb 16 16 2 or 3 pclkb 000a 8334h rscan receive buffer receive complete flag register* 2 rmnd0 16 16 2 or 3 pclkb 000a 8338h rscan receive fifo control register 0* 2 rfcc0 16 16 2 or 3 pclkb 000a 833ah rscan receive fifo control register 1* 2 rfcc1 16 16 2 or 3 pclkb 000a 8340h rscan receive fifo status register 0* 2 rfsts0 16 16 2 or 3 pclkb 000a 8342h rscan receive fifo status register 1* 2 rfsts1 16 16 2 or 3 pclkb 000a 8348h rscan receive fifo pointer control register 0* 2 rfpctr0 16 16 2 or 3 pclkb 000a 834ah rscan receive fifo pointer control register 1* 2 rfpctr1 16 16 2 or 3 pclkb 000a 8350h rscan0 transmit/rece ive fifo control register 0l* 2 cfccl0 16 16 2 or 3 pclkb 000a 8352h rscan0 transmit/receiv e fifo control register 0h* 2 cfcch0 16 16 2 or 3 pclkb 000a 8358h rscan0 transmit/receive fifo status register 0* 2 cfsts0 16 16 2 or 3 pclkb 000a 835ch rscan0 transmit/receive fifo pointer control register 0* 2 cfpctr0 16 16 2 or 3 pclkb 000a 8360h rscan receive fifo message lost status register* 2 rfmsts 8 8 1 or 2 pclkb 000a 8361h rscan0 transmit/receive fifo message lost status regis ter* 2 cfmsts 8 8 1 or 2 pclkb 000a 8362h rscan receive fifo interrupt status register* 2 rfists 8 8 1 or 2 pclkb 000a 8363h rscan transmit/receive fifo receive interrupt status r egister* 2 cfists 8 8 1 or 2 pclkb 000a 8364h rscan0 transmit buffer control register 0* 2 tmc0 8 8 1 or 2 pclkb 000a 8365h rscan0 transmit buffer control register 1* 2 tmc1 8 8 1 or 2 pclkb 000a 8366h rscan0 transmit buffer control register 2* 2 tmc2 8 8 1 or 2 pclkb 000a 8367h rscan0 transmit buffer control register 3* 2 tmc3 8 8 1 or 2 pclkb 000a 836ch rscan0 transmit buffer status register 0* 2 tmsts0 8 8 1 or 2 pclkb table 4.1 list of i/o register s (address order) (21/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 55 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 836dh rscan0 transmit buffer status register 1* 2 tmsts1 8 8 1 or 2 pclkb 000a 836eh rscan0 transmit buffer status register 2* 2 tmsts2 8 8 1 or 2 pclkb 000a 836fh rscan0 transmit buffer status register 3* 2 tmsts3 8 8 1 or 2 pclkb 000a 8374h rscan0 transmit buffer transmit request status registe r* 2 tmtrsts 16 16 2 or 3 pclkb 000a 8376h rscan0 transmit buffer transmit complete status regist er* 2 tmtcsts 16 16 2 or 3 pclkb 000a 8378h rscan0 transmit buffer transmit abort status register* 2 tmtasts 16 16 2 or 3 pclkb 000a 837ah rscan0 transmit buffer interrupt enable register* 2 tmiec 16 16 2 or 3 pclkb 000a 837ch rscan0 transmit hist ory buffer control register* 2 thlcc0 16 16 2 or 3 pclkb 000a 8380h rscan0 transmit history buffer status register* 2 thlsts0 16 16 2 or 3 pclkb 000a 8384h rscan0 transmit history buffer pointer control registe r* 2 thlpctr0 16 16 2 or 3 pclkb 000a 8388h rscan global transmit interrupt status register* 2 gtintsts 16 16 2 or 3 pclkb 000a 838ah rscan global ram window control register* 2 grwcr 16 16 2 or 3 pclkb 000a 838ch rscan global test configuration register* 2 gtstcfg 16 16 2 or 3 pclkb 000a 838eh rscan global test control register* 2 gtstctrl 8 8 1 or 2 pclkb 000a 8394h rscan global test protection unlock register* 2 glockk 16 16 2 or 3 pclkb 000a 83a0h rscan receive rule entry register 0al* 2 gaflidl0 16 16 2 or 3 pclkb 000a 83a0h rscan receive buffer register 0al* 2 rmidl0 16 16 2 or 3 pclkb 000a 83a2h rscan receive rule entry register 0ah* 2 gaflidh0 16 16 2 or 3 pclkb 000a 83a2h rscan receive buffer register 0ah* 2 rmidh0 16 16 2 or 3 pclkb 000a 83a4h rscan receive rule entry register 0bl* 2 gaflml0 16 16 2 or 3 pclkb 000a 83a4h rscan receive buffer register 0bl* 2 rmts0 16 16 2 or 3 pclkb 000a 83a6h rscan receive rule entry register 0bh* 2 gaflmh0 16 16 2 or 3 pclkb 000a 83a6h rscan receive buffer register 0bh* 2 rmptr0 16 16 2 or 3 pclkb 000a 83a8h rscan receive rule entry register 0cl* 2 gaflpl0 16 16 2 or 3 pclkb 000a 83a8h rscan receive buffer register 0cl* 2 rmdf00 16 16 2 or 3 pclkb 000a 83aah rscan receive rule entry register 0ch* 2 gaflph0 16 16 2 or 3 pclkb 000a 83aah rscan receive buffer register 0ch* 2 rmdf10 16 16 2 or 3 pclkb 000a 83ach rscan receive rule entry register 1al* 2 gaflidl1 16 16 2 or 3 pclkb 000a 83ach rscan receive buffer register 0dl* 2 rmdf20 16 16 2 or 3 pclkb 000a 83aeh rscan receive rule entry register 1ah* 2 gaflidh1 16 16 2 or 3 pclkb 000a 83aeh rscan receive buffer register 0dh* 2 rmdf30 16 16 2 or 3 pclkb 000a 83b0h rscan receive rule entry register 1bl* 2 gaflml1 16 16 2 or 3 pclkb 000a 83b0h rscan receive buffer register 1al* 2 rmidl1 16 16 2 or 3 pclkb 000a 83b2h rscan receive rule entry register 1bh* 2 gaflmh1 16 16 2 or 3 pclkb 000a 83b2h rscan receive buffer register 1ah* 2 rmidh1 16 16 2 or 3 pclkb 000a 83b4h rscan receive rule entry register 1cl* 2 gaflpl1 16 16 2 or 3 pclkb 000a 83b4h rscan receive buffer register 1bl* 2 rmts1 16 16 2 or 3 pclkb 000a 83b6h rscan receive rule entry register 1ch* 2 gaflph1 16 16 2 or 3 pclkb 000a 83b6h rscan receive buffer register 1bh* 2 rmptr1 16 16 2 or 3 pclkb 000a 83b8h rscan receive rule entry register 2al* 2 gaflidl2 16 16 2 or 3 pclkb 000a 83b8h rscan receive buffer register 1cl* 2 rmdf01 16 16 2 or 3 pclkb 000a 83bah rscan receive rule entry register 2ah* 2 gaflidh2 16 16 2 or 3 pclkb 000a 83bah rscan receive buffer register 1ch* 2 rmdf11 16 16 2 or 3 pclkb 000a 83bch rscan receive rule entry register 2bl* 2 gaflml2 16 16 2 or 3 pclkb 000a 83bch rscan receive buffer register 1dl* 2 rmdf21 16 16 2 or 3 pclkb 000a 83beh rscan receive rule entry register 2bh* 2 gaflmh2 16 16 2 or 3 pclkb 000a 83beh rscan receive buffer register 1dh* 2 rmdf31 16 16 2 or 3 pclkb 000a 83c0h rscan receive rule entry register 2cl* 2 gaflpl2 16 16 2 or 3 pclkb 000a 83c0h rscan receive buffer register 2al* 2 rmidl2 16 16 2 or 3 pclkb 000a 83c2h rscan receive rule entry register 2ch* 2 gaflph2 16 16 2 or 3 pclkb 000a 83c2h rscan receive buffer register 2ah* 2 rmidh2 16 16 2 or 3 pclkb 000a 83c4h rscan receive rule entry register 3al* 2 gaflidl3 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (22/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 56 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 83c4h rscan receive buffer register 2bl* 2 rmts2 16 16 2 or 3 pclkb 000a 83c6h rscan receive rule entry register 3ah* 2 gaflidh3 16 16 2 or 3 pclkb 000a 83c6h rscan receive buffer register 2bh* 2 rmptr2 16 16 2 or 3 pclkb 000a 83c8h rscan receive rule entry register 3bl* 2 gaflml3 16 16 2 or 3 pclkb 000a 83c8h rscan receive buffer register 2cl* 2 rmdf02 16 16 2 or 3 pclkb 000a 83cah rscan receive rule entry register 3bh* 2 gaflmh3 16 16 2 or 3 pclkb 000a 83cah rscan receive buffer register 2ch* 2 rmdf12 16 16 2 or 3 pclkb 000a 83cch rscan receive rule entry register 3cl* 2 gaflpl3 16 16 2 or 3 pclkb 000a 83cch rscan receive buffer register 2dl* 2 rmdf22 16 16 2 or 3 pclkb 000a 83ceh rscan receive rule entry register 3ch* 2 gaflph3 16 16 2 or 3 pclkb 000a 83ceh rscan receive buffer register 2dh* 2 rmdf32 16 16 2 or 3 pclkb 000a 83d0h rscan receive rule entry register 4al* 2 gaflidl4 16 16 2 or 3 pclkb 000a 83d0h rscan receive buffer register 3al* 2 rmidl3 16 16 2 or 3 pclkb 000a 83d2h rscan receive rule entry register 4ah* 2 gaflidh4 16 16 2 or 3 pclkb 000a 83d2h rscan receive buffer register 3ah* 2 rmidh3 16 16 2 or 3 pclkb 000a 83d4h rscan receive rule entry register 4bl* 2 gaflml4 16 16 2 or 3 pclkb 000a 83d4h rscan receive buffer register 3bl* 2 rmts3 16 16 2 or 3 pclkb 000a 83d6h rscan receive rule entry register 4bh* 2 gaflmh4 16 16 2 or 3 pclkb 000a 83d6h rscan receive buffer register 3bh* 2 rmptr3 16 16 2 or 3 pclkb 000a 83d8h rscan receive rule entry register 4cl* 2 gaflpl4 16 16 2 or 3 pclkb 000a 83d8h rscan receive buffer register 3cl* 2 rmdf03 16 16 2 or 3 pclkb 000a 83dah rscan receive rule entry register 4ch* 2 gaflph4 16 16 2 or 3 pclkb 000a 83dah rscan receive buffer register 3ch* 2 rmdf13 16 16 2 or 3 pclkb 000a 83dch rscan receive rule entry register 5al* 2 gaflidl5 16 16 2 or 3 pclkb 000a 83dch rscan receive buffer register 3dl* 2 rmdf23 16 16 2 or 3 pclkb 000a 83deh rscan receive rule entry register 5ah* 2 gaflidh5 16 16 2 or 3 pclkb 000a 83deh rscan receive buffer register 3dh* 2 rmdf33 16 16 2 or 3 pclkb 000a 83e0h rscan receive rule entry register 5bl* 2 gaflml5 16 16 2 or 3 pclkb 000a 83e0h rscan receive buffer register 4al* 2 rmidl4 16 16 2 or 3 pclkb 000a 83e2h rscan receive rule entry register 5bh* 2 gaflmh5 16 16 2 or 3 pclkb 000a 83e2h rscan receive buffer register 4ah* 2 rmidh4 16 16 2 or 3 pclkb 000a 83e4h rscan receive rule entry register 5cl* 2 gaflpl5 16 16 2 or 3 pclkb 000a 83e4h rscan receive buffer register 4bl* 2 rmts4 16 16 2 or 3 pclkb 000a 83e6h rscan receive rule entry register 5ch* 2 gaflph5 16 16 2 or 3 pclkb 000a 83e6h rscan receive buffer register 4bh* 2 rmptr4 16 16 2 or 3 pclkb 000a 83e8h rscan receive rule entry register 6al* 2 gaflidl6 16 16 2 or 3 pclkb 000a 83e8h rscan receive buffer register 4cl* 2 rmdf04 16 16 2 or 3 pclkb 000a 83eah rscan receive rule entry register 6ah* 2 gaflidh6 16 16 2 or 3 pclkb 000a 83eah rscan receive buffer register 4ch* 2 rmdf14 16 16 2 or 3 pclkb 000a 83ech rscan receive rule entry register 6bl* 2 gaflml6 16 16 2 or 3 pclkb 000a 83ech rscan receive buffer register 4dl* 2 rmdf24 16 16 2 or 3 pclkb 000a 83eeh rscan receive rule entry register 6bh* 2 gaflmh6 16 16 2 or 3 pclkb 000a 83eeh rscan receive buffer register 4dh* 2 rmdf34 16 16 2 or 3 pclkb 000a 83f0h rscan receive rule entry register 6cl* 2 gaflpl6 16 16 2 or 3 pclkb 000a 83f0h rscan receive buffer register 5al* 2 rmidl5 16 16 2 or 3 pclkb 000a 83f2h rscan receive rule entry register 6ch* 2 gaflph6 16 16 2 or 3 pclkb 000a 83f2h rscan receive buffer register 5ah* 2 rmidh5 16 16 2 or 3 pclkb 000a 83f4h rscan receive rule entry register 7al* 2 gaflidl7 16 16 2 or 3 pclkb 000a 83f4h rscan receive buffer register 5bl* 2 rmts5 16 16 2 or 3 pclkb 000a 83f6h rscan receive rule entry register 7ah* 2 gaflidh7 16 16 2 or 3 pclkb 000a 83f6h rscan receive buffer register 5bh* 2 rmptr5 16 16 2 or 3 pclkb 000a 83f8h rscan receive rule entry register 7bl* 2 gaflml7 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (23/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 57 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 83f8h rscan receive buffer register 5cl* 2 rmdf05 16 16 2 or 3 pclkb 000a 83fah rscan receive rule entry register 7bh* 2 gaflmh7 16 16 2 or 3 pclkb 000a 83fah rscan receive buffer register 5ch* 2 rmdf15 16 16 2 or 3 pclkb 000a 83fch rscan receive rule entry register 7cl* 2 gaflpl7 16 16 2 or 3 pclkb 000a 83fch rscan receive buffer register 5dl* 2 rmdf25 16 16 2 or 3 pclkb 000a 83feh rscan receive rule entry register 7ch* 2 gaflph7 16 16 2 or 3 pclkb 000a 83feh rscan receive buffer register 5dh* 2 rmdf35 16 16 2 or 3 pclkb 000a 8400h rscan receive rule entry register 8al* 2 gaflidl8 16 16 2 or 3 pclkb 000a 8400h rscan receive buffer register 6al* 2 rmidl6 16 16 2 or 3 pclkb 000a 8402h rscan receive rule entry register 8ah* 2 gaflidh8 16 16 2 or 3 pclkb 000a 8402h rscan receive buffer register 6ah* 2 rmidh6 16 16 2 or 3 pclkb 000a 8404h rscan receive rule entry register 8bl* 2 gaflml8 16 16 2 or 3 pclkb 000a 8404h rscan receive buffer register 6bl* 2 rmts6 16 16 2 or 3 pclkb 000a 8406h rscan receive rule entry register 8bh* 2 gaflmh8 16 16 2 or 3 pclkb 000a 8406h rscan receive buffer register 6bh* 2 rmptr6 16 16 2 or 3 pclkb 000a 8408h rscan receive rule entry register 8cl* 2 gaflpl8 16 16 2 or 3 pclkb 000a 8408h rscan receive buffer register 6cl* 2 rmdf06 16 16 2 or 3 pclkb 000a 840ah rscan receive rule entry register 8ch* 2 gaflph8 16 16 2 or 3 pclkb 000a 840ah rscan receive buffer register 6ch* 2 rmdf16 16 16 2 or 3 pclkb 000a 840ch rscan receive rule entry register 9al* 2 gaflidl9 16 16 2 or 3 pclkb 000a 840ch rscan receive buffer register 6dl* 2 rmdf26 16 16 2 or 3 pclkb 000a 840eh rscan receive rule entry register 9ah* 2 gaflidh9 16 16 2 or 3 pclkb 000a 840eh rscan receive buffer register 6dh* 2 rmdf36 16 16 2 or 3 pclkb 000a 8410h rscan receive rule entry register 9bl* 2 gaflml9 16 16 2 or 3 pclkb 000a 8410h rscan receive buffer register 7al* 2 rmidl7 16 16 2 or 3 pclkb 000a 8412h rscan receive rule entry register 9bh* 2 gaflmh9 16 16 2 or 3 pclkb 000a 8412h rscan receive buffer register 7ah* 2 rmidh7 16 16 2 or 3 pclkb 000a 8414h rscan receive rule entry register 9cl* 2 gaflpl9 16 16 2 or 3 pclkb 000a 8414h rscan receive buffer register 7bl* 2 rmts7 16 16 2 or 3 pclkb 000a 8416h rscan receive rule entry register 9ch* 2 gaflph9 16 16 2 or 3 pclkb 000a 8416h rscan receive buffer register 7bh* 2 rmptr7 16 16 2 or 3 pclkb 000a 8418h rscan receive rule entry register 10al* 2 gaflidl10 16 16 2 or 3 pclkb 000a 8418h rscan receive buffer register 7cl* 2 rmdf07 16 16 2 or 3 pclkb 000a 841ah rscan receive rule entry register 10ah* 2 gaflidh10 16 16 2 or 3 pclkb 000a 841ah rscan receive buffer register 7ch* 2 rmdf17 16 16 2 or 3 pclkb 000a 841ch rscan receive rule entry register 10bl* 2 gaflml10 16 16 2 or 3 pclkb 000a 841ch rscan receive buffer register 7dl* 2 rmdf27 16 16 2 or 3 pclkb 000a 841eh rscan receive rule entry register 10bh* 2 gaflmh10 16 16 2 or 3 pclkb 000a 841eh rscan receive buffer register 7dh* 2 rmdf37 16 16 2 or 3 pclkb 000a 8420h rscan receive rule entry register 10cl* 2 gaflpl10 16 16 2 or 3 pclkb 000a 8420h rscan receive buffer register 8al* 2 rmidl8 16 16 2 or 3 pclkb 000a 8422h rscan receive rule entry register 10ch* 2 gaflph10 16 16 2 or 3 pclkb 000a 8422h rscan receive buffer register 8ah* 2 rmidh8 16 16 2 or 3 pclkb 000a 8424h rscan receive rule entry register 11al* 2 gaflidl11 16 16 2 or 3 pclkb 000a 8424h rscan receive buffer register 8bl* 2 rmts8 16 16 2 or 3 pclkb 000a 8426h rscan receive rule entry register 11ah* 2 gaflidh11 16 16 2 or 3 pclkb 000a 8426h rscan receive buffer register 8bh* 2 rmptr8 16 16 2 or 3 pclkb 000a 8428h rscan receive rule entry register 11bl* 2 gaflml11 16 16 2 or 3 pclkb 000a 8428h rscan receive buffer register 8cl* 2 rmdf08 16 16 2 or 3 pclkb 000a 842ah rscan receive rule entry register 11bh* 2 gaflmh11 16 16 2 or 3 pclkb 000a 842ah rscan receive buffer register 8ch* 2 rmdf18 16 16 2 or 3 pclkb 000a 842ch rscan receive rule entry register 11cl* 2 gaflpl11 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (24/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 58 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 842ch rscan receive buffer register 8dl* 2 rmdf28 16 16 2 or 3 pclkb 000a 842eh rscan receive rule entry register 11ch* 2 gaflph11 16 16 2 or 3 pclkb 000a 842eh rscan receive buffer register 8dh* 2 rmdf38 16 16 2 or 3 pclkb 000a 8430h rscan receive rule entry register 12al* 2 gaflidl12 16 16 2 or 3 pclkb 000a 8430h rscan receive buffer register 9al* 2 rmidl9 16 16 2 or 3 pclkb 000a 8432h rscan receive rule entry register 12ah* 2 gaflidh12 16 16 2 or 3 pclkb 000a 8432h rscan receive buffer register 9ah* 2 rmidh9 16 16 2 or 3 pclkb 000a 8434h rscan receive rule entry register 12bl* 2 gaflml12 16 16 2 or 3 pclkb 000a 8434h rscan receive buffer register 9bl* 2 rmts9 16 16 2 or 3 pclkb 000a 8436h rscan receive rule entry register 12bh* 2 gaflmh12 16 16 2 or 3 pclkb 000a 8436h rscan receive buffer register 9bh* 2 rmptr9 16 16 2 or 3 pclkb 000a 8438h rscan receive rule entry register 12cl* 2 gaflpl12 16 16 2 or 3 pclkb 000a 8438h rscan receive buffer register 9cl* 2 rmdf09 16 16 2 or 3 pclkb 000a 843ah rscan receive rule entry register 12ch* 2 gaflph12 16 16 2 or 3 pclkb 000a 843ah rscan receive buffer register 9ch* 2 rmdf19 16 16 2 or 3 pclkb 000a 843ch rscan receive rule entry register 13al* 2 gaflidl13 16 16 2 or 3 pclkb 000a 843ch rscan receive buffer register 9dl* 2 rmdf29 16 16 2 or 3 pclkb 000a 843eh rscan receive rule entry register 13ah* 2 gaflidh13 16 16 2 or 3 pclkb 000a 843eh rscan receive buffer register 9dh* 2 rmdf39 16 16 2 or 3 pclkb 000a 8440h rscan receive rule entry register 13bl* 2 gaflml13 16 16 2 or 3 pclkb 000a 8440h rscan receive buffer register 10al* 2 rmidl10 16 16 2 or 3 pclkb 000a 8442h rscan receive rule entry register 13bh* 2 gaflmh13 16 16 2 or 3 pclkb 000a 8442h rscan receive buffer register 10ah* 2 rmidh10 16 16 2 or 3 pclkb 000a 8444h rscan receive rule entry register 13cl* 2 gaflpl13 16 16 2 or 3 pclkb 000a 8444h rscan receive buffer register 10bl* 2 rmts10 16 16 2 or 3 pclkb 000a 8446h rscan receive rule entry register 13ch* 2 gaflph13 16 16 2 or 3 pclkb 000a 8446h rscan receive buffer register 10bh* 2 rmptr10 16 16 2 or 3 pclkb 000a 8448h rscan receive rule entry register 14al* 2 gaflidl14 16 16 2 or 3 pclkb 000a 8448h rscan receive buffer register 10cl* 2 rmdf010 16 16 2 or 3 pclkb 000a 844ah rscan receive rule entry register 14ah* 2 gaflidh14 16 16 2 or 3 pclkb 000a 844ah rscan receive buffer register 10ch* 2 rmdf110 16 16 2 or 3 pclkb 000a 844ch rscan receive rule entry register 14bl* 2 gaflml14 16 16 2 or 3 pclkb 000a 844ch rscan receive buffer register 10dl* 2 rmdf210 16 16 2 or 3 pclkb 000a 844eh rscan receive rule entry register 14bh* 2 gaflmh14 16 16 2 or 3 pclkb 000a 844eh rscan receive buffer register 10dh* 2 rmdf310 16 16 2 or 3 pclkb 000a 8450h rscan receive rule entry register 14cl* 2 gaflpl14 16 16 2 or 3 pclkb 000a 8450h rscan receive buffer register 11al* 2 rmidl11 16 16 2 or 3 pclkb 000a 8452h rscan receive rule entry register 14ch* 2 gaflph14 16 16 2 or 3 pclkb 000a 8452h rscan receive buffer register 11ah* 2 rmidh11 16 16 2 or 3 pclkb 000a 8454h rscan receive rule entry register 15al* 2 gaflidl15 16 16 2 or 3 pclkb 000a 8454h rscan receive buffer register 11bl* 2 rmts11 16 16 2 or 3 pclkb 000a 8456h rscan receive rule entry register 15ah* 2 gaflidh15 16 16 2 or 3 pclkb 000a 8456h rscan receive buffer register 11bh* 2 rmptr11 16 16 2 or 3 pclkb 000a 8458h rscan receive rule entry register 15bl* 2 gaflml15 16 16 2 or 3 pclkb 000a 8458h rscan receive buffer register 11cl* 2 rmdf011 16 16 2 or 3 pclkb 000a 845ah rscan receive rule entry register 15bh* 2 gaflmh15 16 16 2 or 3 pclkb 000a 845ah rscan receive buffer register 11ch* 2 rmdf111 16 16 2 or 3 pclkb 000a 845ch rscan receive rule entry register 15cl* 2 gaflpl15 16 16 2 or 3 pclkb 000a 845ch rscan receive buffer register 11dl* 2 rmdf211 16 16 2 or 3 pclkb 000a 845eh rscan receive rule entry register 15ch* 2 gaflph15 16 16 2 or 3 pclkb 000a 845eh rscan receive buffer register 11dh* 2 rmdf311 16 16 2 or 3 pclkb 000a 8460h rscan receive buffer register 12al* 2 rmidl12 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (25/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 59 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 8462h rscan receive buffer register 12ah* 2 rmidh12 16 16 2 or 3 pclkb 000a 8464h rscan receive buffer register 12bl* 2 rmts12 16 16 2 or 3 pclkb 000a 8466h rscan receive buffer register 12bh* 2 rmptr12 16 16 2 or 3 pclkb 000a 8468h rscan receive buffer register 12cl* 2 rmdf012 16 16 2 or 3 pclkb 000a 846ah rscan receive buffer register 12ch* 2 rmdf112 16 16 2 or 3 pclkb 000a 846ch rscan receive buffer register 12dl* 2 rmdf212 16 16 2 or 3 pclkb 000a 846eh rscan receive buffer register 12dh* 2 rmdf312 16 16 2 or 3 pclkb 000a 8470h rscan receive buffer register 13al* 2 rmidl13 16 16 2 or 3 pclkb 000a 8472h rscan receive buffer register 13ah* 2 rmidh13 16 16 2 or 3 pclkb 000a 8474h rscan receive buffer register 13bl* 2 rmts13 16 16 2 or 3 pclkb 000a 8476h rscan receive buffer register 13bh* 2 rmptr13 16 16 2 or 3 pclkb 000a 8478h rscan receive buffer register 13cl* 2 rmdf013 16 16 2 or 3 pclkb 000a 847ah rscan receive buffer register 13ch* 2 rmdf113 16 16 2 or 3 pclkb 000a 847ch rscan receive buffer register 13dl* 2 rmdf213 16 16 2 or 3 pclkb 000a 847eh rscan receive buffer register 13dh* 2 rmdf313 16 16 2 or 3 pclkb 000a 8480h rscan receive buffer register 14al* 2 rmidl14 16 16 2 or 3 pclkb 000a 8482h rscan receive buffer register 14ah* 2 rmidh14 16 16 2 or 3 pclkb 000a 8484h rscan receive buffer register 14bl* 2 rmts14 16 16 2 or 3 pclkb 000a 8486h rscan receive buffer register 14bh* 2 rmptr14 16 16 2 or 3 pclkb 000a 8488h rscan receive buffer register 14cl* 2 rmdf014 16 16 2 or 3 pclkb 000a 848ah rscan receive buffer register 14ch* 2 rmdf114 16 16 2 or 3 pclkb 000a 848ch rscan receive buffer register 14dl* 2 rmdf214 16 16 2 or 3 pclkb 000a 848eh rscan receive buffer register 14dh* 2 rmdf314 16 16 2 or 3 pclkb 000a 8490h rscan receive buffer register 15al* 2 rmidl15 16 16 2 or 3 pclkb 000a 8492h rscan receive buffer register 15ah* 2 rmidh15 16 16 2 or 3 pclkb 000a 8494h rscan receive buffer register 15bl* 2 rmts15 16 16 2 or 3 pclkb 000a 8496h rscan receive buffer register 15bh* 2 rmptr15 16 16 2 or 3 pclkb 000a 8498h rscan receive buffer register 15cl* 2 rmdf015 16 16 2 or 3 pclkb 000a 849ah rscan receive buffer register 15ch* 2 rmdf115 16 16 2 or 3 pclkb 000a 849ch rscan receive buffer register 15dl* 2 rmdf215 16 16 2 or 3 pclkb 000a 849eh rscan receive buffer register 15dh* 2 rmdf315 16 16 2 or 3 pclkb 000a 8580h to 000a 859fh rscan ram test register 0 to 15* 2 rpgacc0 to 15 16 16 2 or 3 pclkb 000a 85a0h rscan receive fifo access register 0al* 2 rfidl0 16 16 2 or 3 pclkb 000a 85a0h rscan ram test register 16* 2 rpgacc16 16 16 2 or 3 pclkb 000a 85a2h rscan receive fifo access register 0ah* 2 rfidh0 16 16 2 or 3 pclkb 000a 85a2h rscan ram test register 17* 2 rpgacc17 16 16 2 or 3 pclkb 000a 85a4h rscan receive fifo access register 0bl* 2 rfts0 16 16 2 or 3 pclkb 000a 85a4h rscan ram test register 18* 2 rpgacc18 16 16 2 or 3 pclkb 000a 85a6h rscan receive fifo access register 0bh* 2 rfptr0 16 16 2 or 3 pclkb 000a 85a6h rscan ram test register 19* 2 rpgacc19 16 16 2 or 3 pclkb 000a 85a8h rscan receive fifo access register 0cl* 2 rfdf00 16 16 2 or 3 pclkb 000a 85a8h rscan ram test register 20* 2 rpgacc20 16 16 2 or 3 pclkb 000a 85aah rscan receive fifo access register 0ch* 2 rfdf10 16 16 2 or 3 pclkb 000a 85aah rscan ram test register 21* 2 rpgacc21 16 16 2 or 3 pclkb 000a 85ach rscan receive fifo access register 0dl* 2 rfdf20 16 16 2 or 3 pclkb 000a 85ach rscan ram test register 22* 2 rpgacc22 16 16 2 or 3 pclkb 000a 85aeh rscan receive fifo access register 0dh* 2 rfdf30 16 16 2 or 3 pclkb 000a 85aeh rscan ram test register 23* 2 rpgacc23 16 16 2 or 3 pclkb 000a 85b0h rscan receive fifo access register 1al* 2 rfidl1 16 16 2 or 3 pclkb 000a 85b0h rscan ram test register 24* 2 rpgacc24 16 16 2 or 3 pclkb 000a 85b2h rscan receive fifo access register 1ah* 2 rfidh1 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (26/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 60 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 85b2h rscan ram test register 25* 2 rpgacc25 16 16 2 or 3 pclkb 000a 85b4h rscan receive fifo access register 1bl* 2 rfts1 16 16 2 or 3 pclkb 000a 85b4h rscan ram test register 26* 2 rpgacc26 16 16 2 or 3 pclkb 000a 85b6h rscan receive fifo access register 1bh* 2 rfptr1 16 16 2 or 3 pclkb 000a 85b6h rscan ram test register 27* 2 rpgacc27 16 16 2 or 3 pclkb 000a 85b8h rscan receive fifo access register 1cl* 2 rfdf01 16 16 2 or 3 pclkb 000a 85b8h rscan ram test register 28* 2 rpgacc28 16 16 2 or 3 pclkb 000a 85bah rscan receive fifo access register 1ch* 2 rfdf11 16 16 2 or 3 pclkb 000a 85bah rscan ram test register 29* 2 rpgacc29 16 16 2 or 3 pclkb 000a 85bch rscan receive fifo access register 1dl* 2 rfdf21 16 16 2 or 3 pclkb 000a 85bch rscan ram test register 30* 2 rpgacc30 16 16 2 or 3 pclkb 000a 85beh rscan receive fifo access register 1dh* 2 rfdf31 16 16 2 or 3 pclkb 000a 85beh rscan ram test register 31* 2 rpgacc31 16 16 2 or 3 pclkb 000a 85c0h to 000a 85deh rscan ram test register 32 to 47* 2 rpgacc32 to 47 16 16 2 or 3 pclkb 000a 85e0h rscan0 transmit/receive fifo access register 0al* 2 cfidl0 16 16 2 or 3 pclkb 000a 85e0h rscan ram test register 48* 2 rpgacc48 16 16 2 or 3 pclkb 000a 85e2h rscan0 transmit/receive fifo access register 0ah* 2 cfidh0 16 16 2 or 3 pclkb 000a 85e2h rscan ram test register 49* 2 rpgacc49 16 16 2 or 3 pclkb 000a 85e4h rscan0 transmit/receive fifo access register 0bl* 2 cfts0 16 16 2 or 3 pclkb 000a 85e4h rscan ram test register 50* 2 rpgacc50 16 16 2 or 3 pclkb 000a 85e6h rscan0 transmit/receive fifo access register 0bh* 2 cfptr0 16 16 2 or 3 pclkb 000a 85e6h rscan ram test register 51* 2 rpgacc51 16 16 2 or 3 pclkb 000a 85e8h rscan0 transmit/receive fifo access register 0cl* 2 cfdf00 16 16 2 or 3 pclkb 000a 85e8h rscan ram test register 52* 2 rpgacc52 16 16 2 or 3 pclkb 000a 85eah rscan0 transmit/receive fifo access register 0ch* 2 cfdf10 16 16 2 or 3 pclkb 000a 85eah rscan ram test register 53* 2 rpgacc53 16 16 2 or 3 pclkb 000a 85ech rscan0 transmit/receive fifo access register 0dl* 2 cfdf20 16 16 2 or 3 pclkb 000a 85ech rscan ram test register 54* 2 rpgacc54 16 16 2 or 3 pclkb 000a 85eeh rscan0 transmit/receive fifo access register 0dh* 2 cfdf30 16 16 2 or 3 pclkb 000a 85eeh rscan ram test register 55* 2 rpgacc55 16 16 2 or 3 pclkb 000a 85f0h to 000a 85feh rscan ram test register 56 to 63* 2 rpgacc56 to 63 16 16 2 or 3 pclkb 000a 8600h rscan0 transmit buffer register 0al* 2 tmidl0 16 16 2 or 3 pclkb 000a 8600h rscan ram test register 64* 2 rpgacc64 16 16 2 or 3 pclkb 000a 8602h rscan0 transmit buffer register 0ah* 2 tmidh0 16 16 2 or 3 pclkb 000a 8602h rscan ram test register 65* 2 rpgacc65 16 16 2 or 3 pclkb 000a 8604h rscan ram test register 66* 2 rpgacc66 16 16 2 or 3 pclkb 000a 8606h rscan0 transmit buffer register 0bh* 2 tmptr0 16 16 2 or 3 pclkb 000a 8606h rscan ram test register 67* 2 rpgacc67 16 16 2 or 3 pclkb 000a 8608h rscan0 transmit buffer register 0cl* 2 tmdf00 16 16 2 or 3 pclkb 000a 8608h rscan ram test register 68* 2 rpgacc68 16 16 2 or 3 pclkb 000a 860ah rscan0 transmit buffer register 0ch* 2 tmdf10 16 16 2 or 3 pclkb 000a 860ah rscan ram test register 69* 2 rpgacc69 16 16 2 or 3 pclkb 000a 860ch rscan0 transmit buffer register 0dl* 2 tmdf20 16 16 2 or 3 pclkb 000a 860ch rscan ram test register 70* 2 rpgacc70 16 16 2 or 3 pclkb 000a 860eh rscan0 transmit buffer register 0dh* 2 tmdf30 16 16 2 or 3 pclkb 000a 860eh rscan ram test register 71* 2 rpgacc71 16 16 2 or 3 pclkb 000a 8610h rscan0 transmit buffer register 1al* 2 tmidl1 16 16 2 or 3 pclkb 000a 8610h rscan ram test register 72* 2 rpgacc72 16 16 2 or 3 pclkb 000a 8612h rscan0 transmit buffer register 1ah* 2 tmidh1 16 16 2 or 3 pclkb 000a 8612h rscan ram test register 73* 2 rpgacc73 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (27/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 61 of 133 apr 14, 2017 rx24t group 4. i/o registers 000a 8614h rscan ram test register 74* 2 rpgacc74 16 16 2 or 3 pclkb 000a 8616h rscan0 transmit buffer register 1bh* 2 tmptr1 16 16 2 or 3 pclkb 000a 8616h rscan ram test register 75* 2 rpgacc75 16 16 2 or 3 pclkb 000a 8618h rscan0 transmit buffer register 1cl* 2 tmdf01 16 16 2 or 3 pclkb 000a 8618h rscan ram test register 76* 2 rpgacc76 16 16 2 or 3 pclkb 000a 861ah rscan0 transmit buffer register 1ch* 2 tmdf11 16 16 2 or 3 pclkb 000a 861ah rscan ram test register 77* 2 rpgacc77 16 16 2 or 3 pclkb 000a 861ch rscan0 transmit buffer register 1dl* 2 tmdf21 16 16 2 or 3 pclkb 000a 861ch rscan ram test register 78* 2 rpgacc78 16 16 2 or 3 pclkb 000a 861eh rscan0 transmit buffer register 1dh* 2 tmdf31 16 16 2 or 3 pclkb 000a 861eh rscan ram test register 79* 2 rpgacc79 16 16 2 or 3 pclkb 000a 8620h rscan0 transmit buffer register 2al* 2 tmidl2 16 16 2 or 3 pclkb 000a 8620h rscan ram test register 80* 2 rpgacc80 16 16 2 or 3 pclkb 000a 8622h rscan0 transmit buffer register 2ah* 2 tmidh2 16 16 2 or 3 pclkb 000a 8622h rscan ram test register 81* 2 rpgacc81 16 16 2 or 3 pclkb 000a 8624h rscan ram test register 82* 2 rpgacc82 16 16 2 or 3 pclkb 000a 8626h rscan0 transmit buffer register 2bh* 2 tmptr2 16 16 2 or 3 pclkb 000a 8626h rscan ram test register 83* 2 rpgacc83 16 16 2 or 3 pclkb 000a 8628h rscan0 transmit buffer register 2cl* 2 tmdf02 16 16 2 or 3 pclkb 000a 8628h rscan ram test register 84* 2 rpgacc84 16 16 2 or 3 pclkb 000a 862ah rscan0 transmit buffer register 2ch* 2 tmdf12 16 16 2 or 3 pclkb 000a 862ah rscan ram test register 85* 2 rpgacc85 16 16 2 or 3 pclkb 000a 862ch rscan0 transmit buffer register 2dl* 2 tmdf22 16 16 2 or 3 pclkb 000a 862ch rscan ram test register 86* 2 rpgacc86 16 16 2 or 3 pclkb 000a 862eh rscan0 transmit buffer register 2dh* 2 tmdf32 16 16 2 or 3 pclkb 000a 862eh rscan ram test register 87* 2 rpgacc87 16 16 2 or 3 pclkb 000a 8630h rscan0 transmit buffer register 3al* 2 tmidl3 16 16 2 or 3 pclkb 000a 8630h rscan ram test register 88* 2 rpgacc88 16 16 2 or 3 pclkb 000a 8632h rscan0 transmit buffer register 3ah* 2 tmidh3 16 16 2 or 3 pclkb 000a 8632h rscan ram test register 89* 2 rpgacc89 16 16 2 or 3 pclkb 000a 8634h rscan ram test register 90* 2 rpgacc90 16 16 2 or 3 pclkb 000a 8636h rscan0 transmit buffer register 3bh* 2 tmptr3 16 16 2 or 3 pclkb 000a 8636h rscan ram test register 91* 2 rpgacc91 16 16 2 or 3 pclkb 000a 8638h rscan0 transmit buffer register 3cl* 2 tmdf03 16 16 2 or 3 pclkb 000a 8638h rscan ram test register 92* 2 rpgacc92 16 16 2 or 3 pclkb 000a 863ah rscan0 transmit buffer register 3ch* 2 tmdf13 16 16 2 or 3 pclkb 000a 863ah rscan ram test register 93* 2 rpgacc93 16 16 2 or 3 pclkb 000a 863ch rscan0 transmit buffer register 3dl* 2 tmdf23 16 16 2 or 3 pclkb 000a 863ch rscan ram test register 94* 2 rpgacc94 16 16 2 or 3 pclkb 000a 863eh rscan0 transmit buffer register 3dh* 2 tmdf33 16 16 2 or 3 pclkb 000a 863eh rscan ram test register 95* 2 rpgacc95 16 16 2 or 3 pclkb 000a 8640h to 000a 867eh rscan ram test register 96 to 127* 2 rpgacc96 to 127 16 16 2 or 3 pclkb 000a 8680h rscan0 transmit history buffer access register* 2 thlacc0 16 16 2 or 3 pclkb 000c 1200h mtu3 timer control register tcr 8 8, 16, 32 4 or 5 pclka 000c 1201h mtu4 timer control register tcr 8 8 4 or 5 pclka 000c 1202h mtu3 timer mode register 1 tmdr1 8 8, 16 4 or 5 pclka 000c 1203h mtu4 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1204h mtu3 timer i/o control register h tiorh 8 8, 16, 32 4 or 5 pclka 000c 1205h mtu3 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1206h mtu4 timer i/o control register h tiorh 8 8, 16 4 or 5 pcl ka 000c 1207h mtu4 timer i/o control register l tiorl 8 8 4 or 5 pclka table 4.1 list of i/o register s (address order) (28/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 62 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 1208h mtu3 timer interrupt enable register tier 8 8, 16 4 or 5 p clka 000c 1209h mtu4 timer interrupt enable register tier 8 8 4 or 5 pclka 000c 120ah mtu timer output master enable register a toera 8 8 4 or 5 pclka 000c 120dh mtu timer gate control register tgcra 8 8 4 or 5 pclka 000c 120eh mtu timer output control register 1a tocr1a 8 8, 16 4 or 5 pclka 000c 120fh mtu timer output control register 2a tocr2a 8 8 4 or 5 pcl ka 000c 1210h mtu3 timer counter tcnt 16 16, 32 4 or 5 pclka 000c 1212h mtu4 timer counter tcnt 16 16 4 or 5 pclka 000c 1214h mtu timer period data register a tcdra 16 16, 32 4 or 5 pc lka 000c 1216h mtu timer dead time data register a tddra 16 16 4 or 5 pcl ka 000c 1218h mtu3 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 121ah mtu3 timer general register b tgrb 16 16 4 or 5 pclka 000c 121ch mtu4 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 121eh mtu4 timer general register b tgrb 16 16 4 or 5 pclka 000c 1220h mtu timer subcounters a tcntsa 16 16, 32 4 or 5 pclka 000c 1222h mtu timer period buffer register a tcbra 16 16 4 or 5 pclk a 000c 1224h mtu3 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 1226h mtu3 timer general register d tgrd 16 16 4 or 5 pclka 000c 1228h mtu4 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 122ah mtu4 timer general register d tgrd 16 16 4 or 5 pclka 000c 122ch mtu3 timer status register tsr 8 8, 16 4 or 5 pclka 000c 122dh mtu4 timer status register tsr 8 8 4 or 5 pclka 000c 1230h mtu timer interrupt skipping set register 1a titcr1a 8 8, 16 4 or 5 pclka 000c 1231h mtu timer interrupt skipping counters 1a titcnt1a 8 8 4 or 5 pclka 000c 1232h mtu timer buffer transfer set register a tbtera 8 8 4 or 5 pclka 000c 1234h mtu timer dead time enable register a tdera 8 8 4 or 5 pcl ka 000c 1236h mtu timer output level buffer register a tolbra 8 8 4 or 5 pclka 000c 1238h mtu3 timer buffer operation transfer mode register tbtm 8 8, 16 4 or 5 pclka 000c 1239h mtu4 timer buffer operation transfer mode register tbtm 8 8 4 or 5 pclka 000c 123ah mtu timer interrupt skipping mode register a titmra 8 8 4 or 5 pclka 000c 123bh mtu timer interrupt skipping set register 2a titcr2a 8 8 4 or 5 pclka 000c 123ch mtu timer interrupt skipping counters 2a titcnt2a 8 8 4 or 5 pclka 000c 1240h mtu4 timer a/d converter start request control registe r tadcr 16 16 4 or 5 pclka 000c 1244h mtu4 timer a/d converter start request cycle set regis ter a tadcora 16 16, 32 4 or 5 pclka 000c 1246h mtu4 timer a/d converter start request cycle set regis ter b tadcorb 16 16 4 or 5 pclka 000c 1248h mtu4 timer a/d converter start request cycle set buffe r register a tadcobra 16 16, 32 4 or 5 pclka 000c 124ah mtu4 timer a/d converter start request cycle set buffe r register b tadcobrb 16 16 4 or 5 pclka 000c 124ch mtu3 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 124dh mtu4 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1260h mtu timer waveform control register a twcra 8 8 4 or 5 pcl ka 000c 1270h mtu timer mode register 2a tmdr2a 8 8 4 or 5 pclka 000c 1272h mtu3 timer general register e tgre 16 16 4 or 5 pclka 000c 1274h mtu4 timer general register e tgre 16 16 4 or 5 pclka 000c 1276h mtu4 timer general register f tgrf 16 16 4 or 5 pclka 000c 1280h mtu timer start register a tstra 8 8, 16 4 or 5 pclka 000c 1281h mtu timer synchronous register a tsyra 8 8 4 or 5 pclka 000c 1282h mtu timer counter synchronous start register tcsystr 8 8 4 or 5 pclka 000c 1284h mtu timer read/write enable register a trwera 8 8 4 or 5 p clka 000c 1290h mtu0 noise filter control register 0 nfcr0 8 8 4 or 5 pclk a 000c 1291h mtu1 noise filter control register 1 nfcr1 8 8 4 or 5 pclk a 000c 1292h mtu2 noise filter control register 2 nfcr2 8 8 4 or 5 pclk a table 4.1 list of i/o register s (address order) (29/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 63 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 1293h mtu3 noise filter control register 3 nfcr3 8 8 4 or 5 pclk a 000c 1294h mtu4 noise filter control register 4 nfcr4 8 8 4 or 5 pclk a 000c 1296h mtu9 noise filter control register 9 nfcr9 8 8 4 or 5 pclk a 000c 1299h mtu0 noise filter control register c nfcrc 8 8 4 or 5 pclk a 000c 1300h mtu0 timer control register tcr 8 8, 16, 32 4 or 5 pclka 000c 1301h mtu0 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1302h mtu0 timer i/o control register h tiorh 8 8, 16 4 or 5 pcl ka 000c 1303h mtu0 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1304h mtu0 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka 000c 1306h mtu0 timer counter tcnt 16 16 4 or 5 pclka 000c 1308h mtu0 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 130ah mtu0 timer general register b tgrb 16 16 4 or 5 pclka 000c 130ch mtu0 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 130eh mtu0 timer general register d tgrd 16 16 4 or 5 pclka 000c 1320h mtu0 timer general register e tgre 16 16, 32 4 or 5 pclka 000c 1322h mtu0 timer general register f tgrf 16 16 4 or 5 pclka 000c 1324h mtu0 timer interrupt enable register 2 tier2 8 8, 16 4 or 5 pclka 000c 1326h mtu0 timer buffer operation transfer mode register tbtm 8 8 4 or 5 pclka 000c 1328h mtu0 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1380h mtu1 timer control register tcr 8 8, 16 4 or 5 pclka 000c 1381h mtu1 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1382h mtu1 timer i/o control register tior 8 8 4 or 5 pclka 000c 1384h mtu1 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka 000c 1385h mtu1 timer status register tsr 8 8 4 or 5 pclka 000c 1386h mtu1 timer counter tcnt 16 16 4 or 5 pclka 000c 1388h mtu1 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 138ah mtu1 timer general register b tgrb 16 16 4 or 5 pclka 000c 1390h mtu1 timer input capture control register ticcr 8 8 4 or 5 pclka 000c 1391h mtu1 timer mode register 3 tmdr3 8 8 4 or 5 pclka 000c 1394h mtu1 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 13a0h mtu1 timer longword counter tcntlw 32 32 4 or 5 pclka 000c 13a4h mtu1 timer longword general register tgralw 32 32 4 or 5 p clka 000c 13a8h mtu1 timer longword general register tgrblw 32 32 4 or 5 p clka 000c 1400h mtu2 timer control register tcr 8 8, 16 4 or 5 pclka 000c 1401h mtu2 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1402h mtu2 timer i/o control register tior 8 8 4 or 5 pclka 000c 1404h mtu2 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka 000c 1405h mtu2 timer status register tsr 8 8 4 or 5 pclka 000c 1406h mtu2 timer counter tcnt 16 16 4 or 5 pclka 000c 1408h mtu2 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 140ah mtu2 timer general register b tgrb 16 16 4 or 5 pclka 000c 140ch mtu2 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1580h mtu9 timer control register tcr 8 8, 16, 32 4 or 5 pclka 000c 1581h mtu9 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1582h mtu9 timer i/o control register h tiorh 8 8, 16 4 or 5 pcl ka 000c 1583h mtu9 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1584h mtu9 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka 000c 1586h mtu9 timer counter tcnt 16 16 4 or 5 pclka 000c 1588h mtu9 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 158ah mtu9 timer general register b tgrb 16 16 4 or 5 pclka 000c 158ch mtu9 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 158eh mtu9 timer general register d tgrd 16 16 4 or 5 pclka table 4.1 list of i/o register s (address order) (30/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 64 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 15a0h mtu9 timer general register e tgre 16 16, 32 4 or 5 pclka 000c 15a2h mtu9 timer general register f tgrf 16 16 4 or 5 pclka 000c 15a4h mtu9 timer interrupt enable register 2 tier2 8 8, 16 4 or 5 pclka 000c 15a6h mtu9 timer buffer operation transfer mode register tbtm 8 8 4 or 5 pclka 000c 15a8h mtu9 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1a00h mtu6 timer control register tcr 8 8, 16, 32 4 or 5 pclka 000c 1a01h mtu7 timer control register tcr 8 8 4 or 5 pclka 000c 1a02h mtu6 timer mode register 1 tmdr1 8 8, 16 4 or 5 pclka 000c 1a03h mtu7 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1a04h mtu6 timer i/o control register h tiorh 8 8, 16, 32 4 or 5 pclka 000c 1a05h mtu6 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1a06h mtu7 timer i/o control register h tiorh 8 8, 16 4 or 5 pcl ka 000c 1a07h mtu7 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1a08h mtu6 timer interrupt enable register tier 8 8, 16 4 or 5 p clka 000c 1a09h mtu7 timer interrupt enable register tier 8 8 4 or 5 pclka 000c 1a0ah mtu timer output master enable register b toerb 8 8 4 or 5 pclka 000c 1a0dh mtu timer gate control register tgcrb 8 8 4 or 5 pclka 000c 1a0eh mtu timer output control register 1b tocr1b 8 8, 16 4 or 5 pclka 000c 1a0fh mtu timer output control register 2b tocr2b 8 8 4 or 5 pcl ka 000c 1a10h mtu6 timer counter tcnt 16 16, 32 4 or 5 pclka 000c 1a12h mtu7 timer counter tcnt 16 16 4 or 5 pclka 000c 1a14h mtu timer period data register b tcdrb 16 16, 32 4 or 5 pc lka 000c 1a16h mtu timer dead time data register b tddrb 16 16 4 or 5 pcl ka 000c 1a18h mtu6 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 1a1ah mtu6 timer general register b tgrb 16 16 4 or 5 pclka 000c 1a1ch mtu7 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 1a1eh mtu7 timer general register b tgrb 16 16 4 or 5 pclka 000c 1a20h mtu timer subcounters b tcntsb 16 16, 32 4 or 5 pclka 000c 1a22h mtu timer period buffer register b tcbrb 16 16 4 or 5 pclk a 000c 1a24h mtu6 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 1a26h mtu6 timer general register d tgrd 16 16 4 or 5 pclka 000c 1a28h mtu7 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 1a2ah mtu7 timer general register d tgrd 16 16 4 or 5 pclka 000c 1a2ch mtu6 timer status register tsr 8 8, 16 4 or 5 pclka 000c 1a2dh mtu7 timer status register tsr 8 8 4 or 5 pclka 000c 1a30h mtu timer interrupt skipping set register 1b titcr1b 8 8, 16 4 or 5 pclka 000c 1a31h mtu timer interrupt skipping counters 1b titcnt1b 8 8 4 or 5 pclka 000c 1a32h mtu timer buffer transfer set register b tbterb 8 8 4 or 5 pclka 000c 1a34h mtu timer dead time enable register b tderb 8 8 4 or 5 pcl ka 000c 1a36h mtu timer output level buffer register b tolbrb 8 8 4 or 5 pclka 000c 1a38h mtu6 timer buffer operation transfer mode register tbtm 8 8, 16 4 or 5 pclka 000c 1a39h mtu7 timer buffer operation transfer mode register tbtm 8 8 4 or 5 pclka 000c 1a3ah mtu timer interrupt skipping mode register b titmrb 8 8 4 or 5 pclka 000c 1a3bh mtu timer interrupt skipping set register 2b titcr2b 8 8 4 or 5 pclka 000c 1a3ch mtu timer interrupt skipping counters 2b titcnt2b 8 8 4 or 5 pclka 000c 1a40h mtu7 timer a/d converter start request control registe r tadcr 16 16 4 or 5 pclka 000c 1a44h mtu7 timer a/d converter start request cycle set regis ter a tadcora 16 16, 32 4 or 5 pclka 000c 1a46h mtu7 timer a/d converter start request cycle set regis ter b tadcorb 16 16 4 or 5 pclka 000c 1a48h mtu7 timer a/d converter start request cycle set buffe r register a tadcobra 16 16, 32 4 or 5 pclka 000c 1a4ah mtu7 timer a/d converter start request cycle set buffe r register b tadcobrb 16 16 4 or 5 pclka 000c 1a4ch mtu6 timer control register 2 tcr2 8 8 4 or 5 pclka table 4.1 list of i/o register s (address order) (31/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 65 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 1a4dh mtu7 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1a50h mtu6 timer synchronous clear register tsycr 8 8 4 or 5 pcl ka 000c 1a60h mtu timer waveform control register b twcrb 8 8 4 or 5 pcl ka 000c 1a70h mtu timer mode register 2b tmdr2b 8 8 4 or 5 pclka 000c 1a72h mtu6 timer general register e tgre 16 16 4 or 5 pclka 000c 1a74h mtu7 timer general register e tgre 16 16 4 or 5 pclka 000c 1a76h mtu7 timer general register f tgrf 16 16 4 or 5 pclka 000c 1a80h mtu timer start register b tstrb 8 8, 16 4 or 5 pclka 000c 1a81h mtu timer synchronous register b tsyrb 8 8 4 or 5 pclka 000c 1a84h mtu timer read/write enable register b trwerb 8 8 4 or 5 p clka 000c 1a93h mtu6 noise filter control register 6 nfcr6 8 8 4 or 5 pclk a 000c 1a94h mtu7 noise filter control register 7 nfcr7 8 8 4 or 5 pclk a 000c 1a95h mtu5 noise filter control register 5 nfcr5 8 8 4 or 5 pclk a 000c 1c80h mtu5 timer counter u tcntu 16 16, 32 4 or 5 pclka 000c 1c82h mtu5 timer general register u tgru 16 16 4 or 5 pclka 000c 1c84h mtu5 timer control register u tcru 8 8 4 or 5 pclka 000c 1c85h mtu5 timer control register 2u tcr2u 8 8 4 or 5 pclka 000c 1c86h mtu5 timer i/o control register u tioru 8 8 4 or 5 pclka 000c 1c90h mtu5 timer counter v tcntv 16 16, 32 4 or 5 pclka 000c 1c92h mtu5 timer general register v tgrv 16 16 4 or 5 pclka 000c 1c94h mtu5 timer control register v tcrv 8 8 4 or 5 pclka 000c 1c95h mtu5 timer control register 2v tcr2v 8 8 4 or 5 pclka 000c 1c96h mtu5 timer i/o control register v tiorv 8 8 4 or 5 pclka 000c 1ca0h mtu5 timer counter w tcntw 16 16, 32 4 or 5 pclka 000c 1ca2h mtu5 timer general register w tgrw 16 16 4 or 5 pclka 000c 1ca4h mtu5 timer control register w tcrw 8 8 4 or 5 pclka 000c 1ca5h mtu5 timer control register 2w tcr2w 8 8 4 or 5 pclka 000c 1ca6h mtu5 timer i/o control register w tiorw 8 8 4 or 5 pclka 000c 1cb2h mtu5 timer interrupt enable register tier 8 8 4 or 5 pclka 000c 1cb4h mtu5 timer start register tstr 8 8 4 or 5 pclka 000c 1cb6h mtu5 timer compare match clear register tcntcmpclr 8 8 4 o r 5 pclka 000c 1d30h mtu a/d conversion start request select register 0 tad strgr0 8 8 4 or 5 pclka 000c 1d32h mtu a/d conversion start request select register 1 tads trgr1 8 8 4 or 5 pclka 000c 2000h gpt general pwm timer software start register* 2 gtstr 16 8, 16, 32 4 or 5 pclka 000c 2002h gpt noise filter control register* 2 nfcr 16 16, 32 4 or 5 pclka 000c 2004h gpt general pwm timer hardware source start/stop contr ol register 0* 2 gthscr 16 8, 16, 32 4 or 5 pclka 000c 2006h gpt general pwm timer hardware source clear control register* 2 gthccr 16 8, 16, 32 4 or 5 pclka 000c 2008h gpt general pwm timer hardware start source select register* 2 gthssr 16 8, 16, 32 4 or 5 pclka 000c 200ah gpt general pwm timer ha rdware stop/clear source selec t register* 2 gthpsr 16 8, 16, 32 4 or 5 pclka 000c 200ch gpt general pwm timer write-protection register* 2 gtwp 16 8, 16, 32 4 or 5 pclka 000c 200eh gpt general pwm timer sync register* 2 gtsync 16 8, 16, 32 4 or 5 pclka 000c 2010h gpt general pwm timer external trigger input interrupt register* 2 gtetint 16 8, 16, 32 4 or 5 pclka 000c 2014h gpt general pwm timer buffer operation disable registe r* 2 gtbdr 16 8, 16, 32 4 or 5 pclka 000c 2018h gpt general pwm timer start write-protection register* 2 gtswp 16 8, 16, 32 4 or 5 pclka 000c 201ch gpt general pwm timer clearing write-protection regist er* 2 gtcwp 16 8, 16, 32 4 or 5 pclka 000c 2020h gpt general pwm timer common register write-protection register* 2 gtcmnwp 16 8, 16, 32 4 or 5 pclka 000c 2024h gpt general pwm timer mode register* 2 gtmdr 16 8, 16, 32 4 or 5 pclka 000c 2028h gpt general pwm timer external clock noise filter cont rol register* 2 gtecnfcr 32 8, 16, 32 4 or 5 pclka table 4.1 list of i/o register s (address order) (32/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 66 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 202ch gpt general pwm timer a/d conversion start request sig nal monitor register* 2 gtadsmr 32 8, 16, 32 4 or 5 pclka 000c 2100h gpt0 general pwm timer i/o control register* 2 gtior 16 8, 16, 32 4 or 5 pclka 000c 2102h gpt0 general pwm timer interrupt output setting regist er* 2 gtintad 16 8, 16, 32 4 or 5 pclka 000c 2104h gpt0 general pwm timer control register* 2 gtcr 16 8, 16, 32 4 or 5 pclka 000c 2106h gpt0 general pwm timer buffer enable register* 2 gtber 16 8, 16, 32 4 or 5 pclka 000c 2108h gpt0 general pwm timer count direction register* 2 gtudc 16 8, 16, 32 4 or 5 pclka 000c 210ah gpt0 general pwm timer interrupt and a/d converter sta rt request skipping setting register* 2 gtitc 16 8, 16, 32 4 or 5 pclka 000c 210ch gpt0 general pwm timer status register* 2 gtst 16 8, 16, 32 4 or 5 pclka 000c 210eh gpt0 general pwm timer counter* 2 gtcnt 16 16 4 or 5 pclka 000c 2110h gpt0 general pwm timer compare capture register a* 2 gtccra 16 16, 32 4 or 5 pclka 000c 2112h gpt0 general pwm timer compare capture register b* 2 gtccrb 16 16, 32 4 or 5 pclka 000c 2114h gpt0 general pwm timer compare capture register c* 2 gtccrc 16 16, 32 4 or 5 pclka 000c 2116h gpt0 general pwm timer compare capture register d* 2 gtccrd 16 16, 32 4 or 5 pclka 000c 2118h gpt0 general pwm timer compare capture register e* 2 gtccre 16 16, 32 4 or 5 pclka 000c 211ah gpt0 general pwm timer compare capture register f* 2 gtccrf 16 16, 32 4 or 5 pclka 000c 211ch gpt0 general pwm timer period setting register* 2 gtpr 16 16, 32 4 or 5 pclka 000c 211eh gpt0 general pwm timer period setting buffer register* 2 gtpbr 16 16, 32 4 or 5 pclka 000c 2120h gpt0 general pwm timer period setting double buffer register* 2 gtpdbr 16 16, 32 4 or 5 pclka 000c 2124h gpt0 a/d converter start request timing register a* 2 gtadtra 16 16, 32 4 or 5 pclka 000c 2126h gpt0 a/d converter start request timing buffer registe r a* 2 gtadtbra 16 16, 32 4 or 5 pclka 000c 2128h gpt0 a/d converter start request timing double buffer register a* 2 gtadtdbra 16 16, 32 4 or 5 pclka 000c 212ch gpt0 a/d converter start request timing register b* 2 gtadtrb 16 16, 32 4 or 5 pclka 000c 212eh gpt0 a/d converter start request timing buffer registe r b* 2 gtadtbrb 16 16, 32 4 or 5 pclka 000c 2130h gpt0 a/d converter start request timing double buffer register b* 2 gtadtdbrb 16 16, 32 4 or 5 pclka 000c 2134h gpt0 general pwm timer output negate control register* 2 gtoncr 16 16, 32 4 or 5 pclka 000c 2136h gpt0 general pwm timer dead time control register* 2 gtdtcr 16 16, 32 4 or 5 pclka 000c 2138h gpt0 general pwm timer dead time value register u* 2 gtdvu 16 16, 32 4 or 5 pclka 000c 213ah gpt0 general pwm timer dead time value register d* 2 gtdvd 16 16, 32 4 or 5 pclka 000c 213ch gpt0 general pwm timer dead time buffer register u* 2 gtdbu 16 16, 32 4 or 5 pclka 000c 213eh gpt0 general pwm timer dead time buffer register d* 2 gtdbd 16 16, 32 4 or 5 pclka 000c 2140h gpt0 general pwm timer output protection function stat us register* 2 gtsos 16 16, 32 4 or 5 pclka 000c 2142h gpt0 general pwm timer output protection function temp orary release register* 2 gtsotr 16 16, 32 4 or 5 pclka 000c 2180h gpt1 general pwm timer i/o control register* 2 gtior 16 8, 16, 32 4 or 5 pclka 000c 2182h gpt1 general pwm timer interrupt output setting regist er* 2 gtintad 16 8, 16, 32 4 or 5 pclka 000c 2184h gpt1 general pwm timer control register* 2 gtcr 16 8, 16, 32 4 or 5 pclka 000c 2186h gpt1 general pwm timer buffer enable register* 2 gtber 16 8, 16, 32 4 or 5 pclka 000c 2188h gpt1 general pwm timer count direction register* 2 gtudc 16 8, 16, 32 4 or 5 pclka 000c 218ah gpt1 general pwm timer interrupt and a/d converter sta rt request skipping setting register* 2 gtitc 16 8, 16, 32 4 or 5 pclka 000c 218ch gpt1 general pwm timer status register* 2 gtst 16 8, 16, 32 4 or 5 pclka 000c 218eh gpt1 general pwm timer counter* 2 gtcnt 16 16 4 or 5 pclka 000c 2190h gpt1 general pwm timer compare capture register a* 2 gtccra 16 16, 32 4 or 5 pclka 000c 2192h gpt1 general pwm timer compare capture register b* 2 gtccrb 16 16, 32 4 or 5 pclka 000c 2194h gpt1 general pwm timer compare capture register c* 2 gtccrc 16 16, 32 4 or 5 pclka 000c 2196h gpt1 general pwm timer compare capture register d* 2 gtccrd 16 16, 32 4 or 5 pclka 000c 2198h gpt1 general pwm timer compare capture register e* 2 gtccre 16 16, 32 4 or 5 pclka 000c 219ah gpt1 general pwm timer compare capture register f* 2 gtccrf 16 16, 32 4 or 5 pclka 000c 219ch gpt1 general pwm timer period setting register* 2 gtpr 16 16, 32 4 or 5 pclka 000c 219eh gpt1 general pwm timer period setting buffer register* 2 gtpbr 16 16, 32 4 or 5 pclka table 4.1 list of i/o register s (address order) (33/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 67 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 21a0h gpt1 general pwm timer period setting double buffer register* 2 gtpdbr 16 16, 32 4 or 5 pclka 000c 21a4h gpt1 a/d converter start request timing register a* 2 gtadtra 16 16, 32 4 or 5 pclka 000c 21a6h gpt1 a/d converter start request timing buffer registe r a* 2 gtadtbra 16 16, 32 4 or 5 pclka 000c 21a8h gpt1 a/d converter start request timing double buffer register a* 2 gtadtdbra 16 16, 32 4 or 5 pclka 000c 21ach gpt1 a/d converter start request timing register b* 2 gtadtrb 16 16, 32 4 or 5 pclka 000c 21aeh gpt1 a/d converter start request timing buffer registe r b* 2 gtadtbrb 16 16, 32 4 or 5 pclka 000c 21b0h gpt1 a/d converter start request timing double buffer register b* 2 gtadtdbrb 16 16, 32 4 or 5 pclka 000c 21b4h gpt1 general pwm timer output negate control register* 2 gtoncr 16 16, 32 4 or 5 pclka 000c 21b6h gpt1 general pwm timer dead time control register* 2 gtdtcr 16 16, 32 4 or 5 pclka 000c 21b8h gpt1 general pwm timer dead time value register u* 2 gtdvu 16 16, 32 4 or 5 pclka 000c 21bah gpt1 general pwm timer dead time value register d* 2 gtdvd 16 16, 32 4 or 5 pclka 000c 21bch gpt1 general pwm timer dead time buffer register u* 2 gtdbu 16 16, 32 4 or 5 pclka 000c 21beh gpt1 general pwm timer dead time buffer register d* 2 gtdbd 16 16, 32 4 or 5 pclka 000c 21c0h gpt1 general pwm timer output protection function stat us register* 2 gtsos 16 16, 32 4 or 5 pclka 000c 21c2h gpt1 general pwm timer output protection function temp orary release register* 2 gtsotr 16 16, 32 4 or 5 pclka 000c 2200h gpt2 general pwm timer i/o control register* 2 gtior 16 8, 16, 32 4 or 5 pclka 000c 2202h gpt2 general pwm timer interrupt output setting regist er* 2 gtintad 16 8, 16, 32 4 or 5 pclka 000c 2204h gpt2 general pwm timer control register* 2 gtcr 16 8, 16, 32 4 or 5 pclka 000c 2206h gpt2 general pwm timer buffer enable register* 2 gtber 16 8, 16, 32 4 or 5 pclka 000c 2208h gpt2 general pwm timer count direction register* 2 gtudc 16 8, 16, 32 4 or 5 pclka 000c 220ah gpt2 general pwm timer interrupt and a/d converter sta rt request skipping setting register* 2 gtitc 16 8, 16, 32 4 or 5 pclka 000c 220ch gpt2 general pwm timer status register* 2 gtst 16 8, 16, 32 4 or 5 pclka 000c 220eh gpt2 general pwm timer counter* 2 gtcnt 16 16 4 or 5 pclka 000c 2210h gpt2 general pwm timer compare capture register a* 2 gtccra 16 16, 32 4 or 5 pclka 000c 2212h gpt2 general pwm timer compare capture register b* 2 gtccrb 16 16, 32 4 or 5 pclka 000c 2214h gpt2 general pwm timer compare capture register c* 2 gtccrc 16 16, 32 4 or 5 pclka 000c 2216h gpt2 general pwm timer compare capture register d* 2 gtccrd 16 16, 32 4 or 5 pclka 000c 2218h gpt2 general pwm timer compare capture register e* 2 gtccre 16 16, 32 4 or 5 pclka 000c 221ah gpt2 general pwm timer compare capture register f* 2 gtccrf 16 16, 32 4 or 5 pclka 000c 221ch gpt2 general pwm timer period setting register* 2 gtpr 16 16, 32 4 or 5 pclka 000c 221eh gpt2 general pwm timer period setting buffer register* 2 gtpbr 16 16, 32 4 or 5 pclka 000c 2220h gpt2 general pwm timer period setting double buffer register* 2 gtpdbr 16 16, 32 4 or 5 pclka 000c 2224h gpt2 a/d converter start request timing register a* 2 gtadtra 16 16, 32 4 or 5 pclka 000c 2226h gpt2 a/d converter start request timing buffer registe r a* 2 gtadtbra 16 16, 32 4 or 5 pclka 000c 2228h gpt2 a/d converter start request timing double buffer register a* 2 gtadtdbra 16 16, 32 4 or 5 pclka 000c 222ch gpt2 a/d converter start request timing register b* 2 gtadtrb 16 16, 32 4 or 5 pclka 000c 222eh gpt2 a/d converter start request timing buffer registe r b* 2 gtadtbrb 16 16, 32 4 or 5 pclka 000c 2230h gpt2 a/d converter start request timing double buffer register b* 2 gtadtdbrb 16 16, 32 4 or 5 pclka 000c 2234h gpt2 general pwm timer output negate control register* 2 gtoncr 16 16, 32 4 or 5 pclka 000c 2236h gpt2 general pwm timer dead time control register* 2 gtdtcr 16 16, 32 4 or 5 pclka 000c 2238h gpt2 general pwm timer dead time value register u* 2 gtdvu 16 16, 32 4 or 5 pclka 000c 223ah gpt2 general pwm timer dead time value register d* 2 gtdvd 16 16, 32 4 or 5 pclka 000c 223ch gpt2 general pwm timer dead time buffer register u* 2 gtdbu 16 16, 32 4 or 5 pclka 000c 223eh gpt2 general pwm timer dead time buffer register d* 2 gtdbd 16 16, 32 4 or 5 pclka 000c 2240h gpt2 general pwm timer output protection function stat us register* 2 gtsos 16 16, 32 4 or 5 pclka 000c 2242h gpt2 general pwm timer output protection function temp orary release register* 2 gtsotr 16 16, 32 4 or 5 pclka table 4.1 list of i/o register s (address order) (34/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 68 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 2280h gpt3 general pwm timer i/o control register* 2 gtior 16 8, 16, 32 4 or 5 pclka 000c 2282h gpt3 general pwm timer interrupt output setting regist er* 2 gtintad 16 8, 16, 32 4 or 5 pclka 000c 2284h gpt3 general pwm timer control register* 2 gtcr 16 8, 16, 32 4 or 5 pclka 000c 2286h gpt3 general pwm timer buffer enable register* 2 gtber 16 8, 16, 32 4 or 5 pclka 000c 2288h gpt3 general pwm timer count direction register* 2 gtudc 16 8, 16, 32 4 or 5 pclka 000c 228ah gpt3 general pwm timer interrupt and a/d converter sta rt request skipping setting register* 2 gtitc 16 8, 16, 32 4 or 5 pclka 000c 228ch gpt3 general pwm timer status register* 2 gtst 16 8, 16, 32 4 or 5 pclka 000c 228eh gpt3 general pwm timer counter* 2 gtcnt 16 16 4 or 5 pclka 000c 2290h gpt3 general pwm timer compare capture register a* 2 gtccra 16 16, 32 4 or 5 pclka 000c 2292h gpt3 general pwm timer compare capture register b* 2 gtccrb 16 16, 32 4 or 5 pclka 000c 2294h gpt3 general pwm timer compare capture register c* 2 gtccrc 16 16, 32 4 or 5 pclka 000c 2296h gpt3 general pwm timer compare capture register d* 2 gtccrd 16 16, 32 4 or 5 pclka 000c 2298h gpt3 general pwm timer compare capture register e* 2 gtccre 16 16, 32 4 or 5 pclka 000c 229ah gpt3 general pwm timer compare capture register f* 2 gtccrf 16 16, 32 4 or 5 pclka 000c 229ch gpt3 general pwm timer period setting register* 2 gtpr 16 16, 32 4 or 5 pclka 000c 229eh gpt3 general pwm timer period setting buffer register* 2 gtpbr 16 16, 32 4 or 5 pclka 000c 22a0h gpt3 general pwm timer period setting double buffer register* 2 gtpdbr 16 16, 32 4 or 5 pclka 000c 22a4h gpt3 a/d converter start request timing register a* 2 gtadtra 16 16, 32 4 or 5 pclka 000c 22a6h gpt3 a/d converter start request timing buffer registe r a* 2 gtadtbra 16 16, 32 4 or 5 pclka 000c 22a8h gpt3 a/d converter start request timing double buffer register a* 2 gtadtdbra 16 16, 32 4 or 5 pclka 000c 22ach gpt3 a/d converter start request timing register b* 2 gtadtrb 16 16, 32 4 or 5 pclka 000c 22aeh gpt3 a/d converter start request timing buffer registe r b* 2 gtadtbrb 16 16, 32 4 or 5 pclka 000c 22b0h gpt3 a/d converter start request timing double buffer register b* 2 gtadtdbrb 16 16, 32 4 or 5 pclka 000c 22b4h gpt3 general pwm timer output negate control register* 2 gtoncr 16 16, 32 4 or 5 pclka 000c 22b6h gpt3 general pwm timer dead time control register* 2 gtdtcr 16 16, 32 4 or 5 pclka 000c 22b8h gpt3 general pwm timer dead time value register u* 2 gtdvu 16 16, 32 4 or 5 pclka 000c 22bah gpt3 general pwm timer dead time value register d* 2 gtdvd 16 16, 32 4 or 5 pclka 000c 22bch gpt3 general pwm timer dead time buffer register u* 2 gtdbu 16 16, 32 4 or 5 pclka 000c 22beh gpt3 general pwm timer dead time buffer register d* 2 gtdbd 16 16, 32 4 or 5 pclka 000c 22c0h gpt3 general pwm timer output protection function stat us register* 2 gtsos 16 16, 32 4 or 5 pclka 000c 22c2h gpt3 general pwm timer output protection function temp orary release register* 2 gtsotr 16 16, 32 4 or 5 pclka 000c 2300h gpt01 general pwm timer longword counter* 2 gtcntlw 32 32 4 or 5 pclka 000c 2304h gpt01 general pwm timer longword compare capture regis ter a* 2 gtccralw 32 32 4 or 5 pclka 000c 2308h gpt01 general pwm timer longword compare capture regis ter b* 2 gtccrblw 32 32 4 or 5 pclka 000c 230ch gpt01 general pwm timer longword compare capture regis ter c* 2 gtccrclw 32 32 4 or 5 pclka 000c 2310h gpt01 general pwm timer longword compare capture regis ter d* 2 gtccrdlw 32 32 4 or 5 pclka 000c 2314h gpt01 general pwm timer longword compare capture regis ter e* 2 gtccrelw 32 32 4 or 5 pclka 000c 2318h gpt01 general pwm timer longword compare capture regis ter f* 2 gtccrflw 32 32 4 or 5 pclka 000c 231ch gpt01 general pwm timer longword period setting regist er* 2 gtprlw 32 32 4 or 5 pclka 000c 2320h gpt01 general pwm timer longword period setting buffer register* 2 gtpbrlw 32 32 4 or 5 pclka 000c 2324h gpt01 general pwm timer longword period setting double buffer register* 2 gtpdbrlw 32 32 4 or 5 pclka 000c 2328h gpt01 longword a/d converter start request timing regi ster a* 2 gtadtralw 32 32 4 or 5 pclka 000c 232ch gpt01 longword a/d conve rter start request timing buff er register a* 2 gtadtbralw 32 32 4 or 5 pclka table 4.1 list of i/o register s (address order) (35/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 69 of 133 apr 14, 2017 rx24t group 4. i/o registers 000c 2330h gpt01 longword a/d converter start request timing doub le buffer register a* 2 gtadtdbral w 32 32 4 or 5 pclka 000c 2334h gpt01 longword a/d converter start request timing regi ster b* 2 gtadtrblw 32 32 4 or 5 pclka 000c 2338h gpt01 longword a/d converter start request timing buff er register b* 2 gtadtbrblw 32 32 4 or 5 pclka 000c 233ch gpt01 longword a/d converter start request timing doub le buffer register b* 2 gtadtdbrbl w 32 32 4 or 5 pclka 000c 2340h gpt01 general pwm timer longword dead time value register u* 2 gtdvulw 32 32 4 or 5 pclka 000c 2344h gpt01 general pwm timer longword dead time value register d* 2 gtdvdlw 32 32 4 or 5 pclka 000c 2348h gpt01 general pwm timer longword dead time buffer regi ster u* 2 gtdbulw 32 32 4 or 5 pclka 000c 234ch gpt01 general pwm timer longword dead time buffer regi ster d* 2 gtdbdlw 32 32 4 or 5 pclka 000c 2380h gpt23 general pwm timer longword counter* 2 gtcntlw 32 32 4 or 5 pclka 000c 2384h gpt23 general pwm timer longword compare capture regis ter a* 2 gtccralw 32 32 4 or 5 pclka 000c 2388h gpt23 general pwm timer longword compare capture regis ter b* 2 gtccrblw 32 32 4 or 5 pclka 000c 238ch gpt23 general pwm timer longword compare capture regis ter c* 2 gtccrclw 32 32 4 or 5 pclka 000c 2390h gpt23 general pwm timer longword compare capture regis ter d* 2 gtccrdlw 32 32 4 or 5 pclka 000c 2394h gpt23 general pwm timer longword compare capture regis ter e* 2 gtccrelw 32 32 4 or 5 pclka 000c 2398h gpt23 general pwm timer longword compare capture regis ter f* 2 gtccrflw 32 32 4 or 5 pclka 000c 239ch gpt23 general pwm timer longword period setting regist er* 2 gtprlw 32 32 4 or 5 pclka 000c 23a0h gpt23 general pwm timer longword period setting buffer register* 2 gtpbrlw 32 32 4 or 5 pclka 000c 23a4h gpt23 general pwm timer longword period setting double buffer register* 2 gtpdbrlw 32 32 4 or 5 pclka 000c 23a8h gpt23 longword a/d converter start request timing regi ster a* 2 gtadtralw 32 32 4 or 5 pclka 000c 23ach gpt23 longword a/d converter start request timing buff er register a* 2 gtadtbralw 32 32 4 or 5 pclka 000c 23b0h gpt23 longword a/d converter start request timing doub le buffer register a* 2 gtadtdbral w 32 32 4 or 5 pclka 000c 23b4h gpt23 longword a/d converter start request timing regi ster b* 2 gtadtrblw 32 32 4 or 5 pclka 000c 23b8h gpt23 longword a/d converter start request timing buff er register b* 2 gtadtbrblw 32 32 4 or 5 pclka 000c 23bch gpt23 longword a/d converter start request timing doub le buffer register b* 2 gtadtdbrbl w 32 32 4 or 5 pclka 000c 23c0h gpt23 general pwm timer longword dead time value register u* 2 gtdvulw 32 32 4 or 5 pclka 000c 23c4h gpt23 general pwm timer longword dead time value register d* 2 gtdvdlw 32 32 4 or 5 pclka 000c 23c8h gpt23 general pwm timer longword dead time buffer regi ster u* 2 gtdbulw 32 32 4 or 5 pclka 000c 23cch gpt23 general pwm timer longword dead time buffer regi ster d* 2 gtdbdlw 32 32 4 or 5 pclka 007f c090h flash e2 dataflash control register dflctl 8 8 2 or 3 fclk 007f c100h flash flash p/e mode control register fpmcr 8 8 2 or 3 fcl k 007f c104h flash flash area select register fasr 8 8 2 or 3 fclk 007f c108h flash flash processing start address register l fsarl 16 16 2 or 3 fclk 007f c110h flash flash processing start address register h fsarh 16 16 2 or 3 fclk 007f c114h flash flash control register fcr 8 8 2 or 3 fclk 007f c118h flash flash processing end address register l fearl 16 16 2 or 3 fclk 007f c120h flash flash processing end address register h fearh 16 16 2 or 3 fclk 007f c124h flash flash reset register fresetr 8 8 2 or 3 fclk 007f c12ch flash flash status register 1 fstatr1 8 8 2 or 3 fclk 007f c130h flash flash write buffer 0 register fwb0 16 16 2 or 3 fclk 007f c138h flash flash write buffer 1 register fwb1 16 16 2 or 3 fclk 007f c140h flash flash write buffer 2 register fwb2 16 16 2 or 3 fclk table 4.1 list of i/o register s (address order) (36/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 70 of 133 apr 14, 2017 rx24t group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. when a ccessing a register in 16-bit units, access the address of the tmr0, tmr2, tmr4, or tmr6 register. table 23.5 lists register allocation for 16-bit access in the users manua l: hardware. note 2. this register is not available for chip version a. 007f c144h flash flash write buffer 3 register fwb3 16 16 2 or 3 fclk 007f c180h flash protection unlock register fpr 8 8 2 or 3 fclk 007f c184h flash protection unlock status register fpsr 8 8 2 or 3 fc lk 007f c1c0h flash flash start-up setting monitor register fscmr 16 16 2 or 3 fclk 007f c1c8h flash flash access window start address monitor regist er fawsmr 16 16 2 or 3 fclk 007f c1d0h flash flash access window end address monitor register fawemr 16 16 2 or 3 fclk 007f c1d8h flash flash initial setting register fisr 8 8 2 or 3 fclk 007f c1dch flash flash extra area co ntrol register fexcr 8 8 2 or 3 f clk 007f c1e0h flash flash error address monitor register l feaml 16 16 2 or 3 fclk 007f c1e8h flash flash error address monitor register h feamh 16 16 2 or 3 fclk 007f c1f0h flash flash status register 0 fstatr0 8 8 2 or 3 fclk 007f c350h flashcon st unique id register 0 uidr0 32 32 2 or 3 fclk 007f c354h flashcon st unique id register 1 uidr1 32 32 2 or 3 fclk 007f c358h flashcon st unique id register 2 uidr2 32 32 2 or 3 fclk 007f c35ch flashcon st unique id register 3 uidr3 32 32 2 or 3 fclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 or 3 f clk table 4.1 list of i/o register s (address order) (37/37) address module symbol register name register symbol number of bits access size number of access cycles iclk pclk
r01ds0257ej0200 rev.2.00 page 71 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the mcu may result if absolute max imum ratings are exceeded. to preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the vcc an d vss pins, between the avcc0 and avss0 pins, between the avcc1 a nd avss1 pins, between the avcc2 and avss2 pins, between the vref and avss2 pins. place capacitors of about 0.1 f as close as possible to every power supply pin and use the shortest and heaviest possible traces. connect the vcl pin to a vss pin via a 4.7 f capacitor. the ca pacitor must be placed close to the pin. do not input signals or an i/o pull-up power supply to ports ot her than 5-v tolerant ports while the device is not powered. the current injection that results from input of such a signal or i/o pull-up may cause malfunction and the abnormal current t hat passes in the device at this time may cause degradation of inte rnal elements. even if C0.3 to +6.5 v is input to 5-v tolerant ports, it will not cause problems such as damage to the mcu. note 1. ports b1 and b2 are 5 v tolerant. note 1. avcc0/avcc1/avcc2/vref and vcc can be set individually w ithin the operating range. note 2. when powering on the vcc and avcc0/avcc1/avcc2/vref pins , power them on at the same time or the vcc pin first and then the avcc0/avcc1/avcc2/vref pin. table 5.1 absolute maximum ratings conditions: vss = avss0 = avss1 = avss2 = 0 v item symbol value unit power supply voltage vcc C0.3 to +6.5 v input voltage port 4, port 5, port 6 v in C0.3 to vref + 0.3 v except for port 4, port 5, port 6 and ports for 5 v tolerant* 1 C0.3 to vcc + 0.3 v ports for 5 v tolerant* 1 C0.3 to +6.5 v analog power supply voltage avcc0, avcc1, avcc2, vref C0.3 to +6.5 v analog input voltage when an000 to an003, an100 to an103, an200 to an211 used v an C0.3 to vref + 0.3 v when an016, an116, cvrefc0, cvrefc1 used C0.3 to vcc + 0.3 operating temperature t opr C40 to +85 c storage temperature t stg C55 to +125 c table 5.2 recommended operating voltage conditions item symbol conditions min. typ. max. unit power supply voltages vcc *1, *2 2.7 5.5 v vss 0 analog power supply voltages avcc0, avcc1, avcc2, vref *1, *2 vcc 5.5 v avss0, avss1, avss2 0
r01ds0257ej0200 rev.2.00 page 72 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics 5.2 dc characteristics table 5.3 dc characteristics (1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus, 5 v tolerant) v ih vcc 0.7 5.8 v ports b1, b2 (5 v tolerant) vcc 0.8 5.8 ports 00 to 02, ports 10, 11, ports 20 to 24, ports 30 to 33, 36, 37, ports 70 to 76, ports 80 to 82, ports 90 to 96, ports a0 to a5, port b0, ports b3 to b7, ports d0 to d7, ports e0 to e5, res# vcc 0.8 vcc + 0.3 ports 40 to 47, ports 50 to 55, ports 60 to 65 vref 0.8 vref + 0.3 riic input pin (except for smbus) v il C0.3 vcc 0.3 ports 40 to 47, ports 50 to 55, ports 60 to 65 C0.3 vref 0.2 other than riic input pin, other than ports 40 to 47, 50 to 55, or 60 to 65 C0.3 vcc 0.2 riic input pin (except for smbus) v t vcc 0.05 ports 40 to 47, ports 50 to 55, ports 60 to 65 vref 0.1 other than riic input pin, other than ports 40 to 47, 50 to 55, or 60 to 65 vcc 0.1 input level voltage (except for schmitt trigger input pins) md v ih vcc 0.9 vcc + 0.3 v extal (external clock input) vcc 0.8 vcc + 0.3 riic input pin (smbus) 2.1 vcc + 0.3 vcc 5.2 v md v il C0.3 vcc 0.1 extal (external clock input) C0.3 vcc 0.2 riic input pin (smbus) C0.3 0.8 vcc 5.2 v
r01ds0257ej0200 rev.2.00 page 73 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics table 5.5 dc characteristics (3) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c table 5.4 dc characteristics (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions input leakage current res#, md, port e2 | i in | 1.0 a v in = 0 v, vcc three-state leakage current (off-state) port 4, port 5, port 6 | i tsi | 1.0 a v in = 0 v, vref ports except for 5-v tolerant ports and port 4, port 5, port 6 0.2 v in = 0 v, vcc ports for 5 v tolerant 1.0 v in = 0 v, 5.8 v input capacitance all input pins c in 4 15 pf v in = 0 mv, f = 1 mhz, t a = 25c input pull-up resistor all ports (except for port e2) r u 10 20 50 k v in = 0 v item symbol chip version a chip version b unit test conditions typ. * 7 max. typ. * 7 max. supply current * 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 80 mhz i cc 26.0 26.0 ma iclk = 64 mhz 20.7 20.7 iclk = 32 mhz 11.8 11.8 iclk = 16 mhz 7.0 7.0 iclk = 8 mhz 4.7 4.7 all peripheral operation: normal iclk = 80 mhz* 3 35.0 40.5 iclk = 64 mhz* 4 28.5 32.5 iclk = 32 mhz* 5 18.5 20.9 iclk = 16 mhz* 5 10.5 11.7 iclk = 8 mhz* 5 6.4 7.0 all peripheral operation: max. iclk = 80 mhz* 3 70.0 80.0 iclk = 64 mhz* 4 60.0 70.0 iclk = 32 mhz* 5 40.0 45.0 sleep mode no peripheral operation* 2 iclk = 80 mhz 7.2 7.2 iclk = 64 mhz 6.1 6.1 iclk = 32 mhz 4.4 4.4 iclk = 16 mhz 3.4 3.4 iclk = 8 mhz 2.9 2.9 all peripheral operation: normal iclk = 80 mhz* 3 22.4 26.9 iclk = 64 mhz* 4 18.4 21.9 iclk = 32 mhz* 5 13.5 15.5 iclk = 16 mhz* 5 8.0 9.0 iclk = 8 mhz* 5 5.2 5.7
r01ds0257ej0200 rev.2.00 page 74 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics note 1. supply current values do not include output charge/disch arge current from all pins. the values apply when internal pull -up moss are in the off state. note 2. supply of the clock signal to peripheral modules is stopped in this state. the clock source is pll. fclk, pclka, pclkb, and pclkd are set to divided by 64. note 3. the clock signal to per ipheral modules is supplied in th is state. the clock source is p ll. fclk is set to divided by 4. pclka is set to divided by 1. pclkb and pclkd are set to divided by 2. note 4. the clock signal to per ipheral modules is supplied in th is state. the clock source is p ll. pclka is set to divided by 1 . fclk, pclkb, and pclkd are set to divided by 2. note 5. the clock signal to per ipheral modules is supplied in th is state. the clock source is p ll. the frequencies of fclk, pcl ka, pclkb, and pclkd are same as iclk. note 6. this is the increase when data is programmed to or erase d from the rom or e2 dataflash during program execution. note 7. values when vcc = 5 v. note 8. supply of the clock signal to peripheral modules is stopped in this state. the clock source is pll. fclk, pclka, pclkb, and pclkd are set to divided by 64. note 9. supply of the clock signal to peripheral modules is stopped in this state. the clock sour ce is pll. the frequencies of fclk, pclka, pclkb, and pclkd are same as iclk. note 10. when the frequency of pll is 48 mhz. supply current * 1 high-speed operating mode deep sleep mode no peripheral operation* 2 iclk = 80 mhz i cc 3.4 3.4 ma iclk = 64 mhz 2.9 2.9 iclk = 32 mhz 2.5 2.5 iclk = 16 mhz 2.3 2.3 iclk = 8 mhz 2.2 2.2 all peripheral operation: normal iclk = 80 mhz* 3 17.7 22.2 iclk = 64 mhz* 4 14.4 17.9 iclk = 32 mhz* 5 10.9 12.9 iclk = 16 mhz* 5 6.6 7.6 iclk = 8 mhz* 5 4.3 4.8 increase during bgo operation* 6 2.5 2.5 middle-speed operating modes normal operating mode no peripheral operation* 8 iclk = 12 mhz* 10 i cc 5.3 5.3 ma iclk = 8 mhz 4.5 4.5 iclk = 1 mhz 2.5 2.5 all peripheral operation: normal* 9 iclk = 12 mhz* 10 7.8 8.7 iclk = 8 mhz 6.3 6.9 iclk = 1 mhz 2.7 2.7 all peripheral operation: max.* 9 iclk = 12 mhz* 10 17.0 18.0 sleep mode no peripheral operation* 8 iclk = 12 mhz* 10 2.6 2.6 iclk = 8 mhz 2.7 2.7 iclk = 1 mhz 2.2 2.2 all peripheral operation: normal* 9 iclk = 12 mhz* 10 6.0 6.7 iclk = 8 mhz 5.1 5.6 iclk = 1 mhz 2.5 2.5 deep sleep mode no peripheral operation* 8 iclk = 12 mhz* 10 1.8 1.8 iclk = 8 mhz 2.1 2.1 iclk = 1 mhz 2.1 2.1 all peripheral operation: normal* 9 iclk = 12 mhz* 10 5.0 5.7 iclk = 8 mhz 4.3 4.8 iclk = 1 mhz 2.3 2.3 increase during bgo operation* 6 2.5 2.5 item symbol chip version a chip version b unit test conditions typ. * 7 max. typ. * 7 max.
r01ds0257ej0200 rev.2.00 page 75 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 5 v. figure 5.1 voltage dependency in software standby mode (chip ver sion a) (reference data) table 5.6 dc characteristics (4) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol chip version a chip version b unit test conditions typ.* 3 max. typ.* 3 max. supply current* 1 software standby mode* 2 t a = 25c i cc 1.0 55.0 1.5 15.0 a t a = 55c 1.5 60.0 3.0 38.0 t a = 85c 5.5 260.0 13.0 135.0 3.5 4 4.5 5 5.5 3 icc ( a) 1 10 100 vcc(v) ta = 85c *2 ta = 85c *1 ta = 55c *2 ta = 55c *1 ta = 25c *2 ta = 25c *1 ta = 25c *2 ta = 25c *1 ta = 55c *2 ta = 55c *1 ta = 85c *2 ta = 85c *1 *1 average value of the tested middle samples during product eva luation. *2 average value of the tested upper-limit samples during produc t evaluation.
r01ds0257ej0200 rev.2.00 page 76 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics figure 5.2 voltage dependency in software standby mode (chip ver sion b) (reference data) 3.5 4 4.5 5 3 icc ( a) 0.1 10 100 vcc (v) 5.5 1 ta = 25c *2 ta = 25c *1 ta = 55c *2 ta = 55c *1 ta = 85c *2 ta = 85c *1 *1 average value of the tested middle samples during product eva luation. *2 average value of the tested upper-limit samples during produc t evaluation. ta = 85c *2 ta = 85c *1 ta = 55c *2 ta = 55c *1 ta = 25c *2 ta = 25c *1
r01ds0257ej0200 rev.2.00 page 77 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics figure 5.3 temperature dependency in software standby mode (chip version a) (reference data) figure 5.4 temperature dependency in software standby mode (chip version b) (reference data) -40 -20 0 20 40 60 80 100 0.1 1 10 100 ta (c) icc ( a) average value of the tested middle samples during product evalu ation. average value of the tested upper-limit samples during product evaluation. -40 -20 0 20 40 60 80 100 0.01 0.10 1.00 10.00 icc ( a) 100.00 average value of the tested middle samples during product evalu ation. average value of the tested upper-limit samples during product evaluation. ta (c)
r01ds0257ej0200 rev.2.00 page 78 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics note 1. total power dissipated by the entire chip (including out put currents) note 1. the value of the d/a converter is the value of the power supply current including the reference current. note 2. when vcc =avcc0 = avcc1 = avcc2 = vref = 5 v. note 3. current consumed only by the comparator c module. note 1. when ofs1.lvdas = 0. note 2. turn on the power supply voltage according to the normal startup rising gradient because the register settings set by o fs1 are not read in boot mode. table 5.7 dc characteristics (5) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol typ. max. unit test conditions permissible total consumption power* 1 pd 570 mw table 5.8 dc characteristics (6) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ.* 2 max. unit test conditions analog power supply current a/d unit 0 during a/d conversion (programmable gain amplifier in use) i avcc 1.52.5ma during a/d conversion (programmable gain amplifier not in use) 1.01.8 a/d unit 1 during a/d conversion (sample- and-hold circuits in use, programmable gain amplifier in use) 4.66.9 during a/d conversion (sample- and-hold circuits in use, programmable gain amplifier not in use) 3.14.8 during a/d conversion (sample- and-hold circuits not in use, programmable gain amplifier in use) 2.53.9 during a/d conversion (sample- and-hold circuits not in use, programmable gain amplifier not in use) 1.01.8 a/d unit 2 1.0 1.8 during d/a conversion (per channel)* 1 0.71.0 waiting for a/d or d/a conversion (all units) 2.2 a waiting for a/d conversion (all units) 1.2 a comparator c operating current* 3 comparator enabled i cmp 40.0 60.0 a table 5.9 dc characteristics (7) conditions: vcc = 0 v to avcc0, avcc0 = avcc1 = avcc2 = vref = 0 v to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions power-on vcc rising gradient at normal startup srvcc 0.02 20 ms/v voltage monitoring 0 reset enabled at startup* 1, * 2 0.02
r01ds0257ej0200 rev.2.00 page 79 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics figure 5.5 ripple waveform note: the recommended capacitance i s 4.7 f. variations in conne cted capacitors should be within the above range. table 5.10 dc characteristics (8) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c the ripple voltage must meet the allowable ripple frequency f r (vcc) within the range between the vcc upper limit (5.5 v) and lower limit (2.7 v). when vcc change exceeds vcc 10%, the allo wable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r (vcc) 10 khz figure 5.5 v r (vcc) vcc 0.2 1 mhz figure 5.5 v r (vcc) vcc 0.08 10 mhz figure 5.5 v r (vcc) vcc 0.06 allowable voltage change rising/falling gradient dt/dvcc 1.0 ms/v when vcc change exceeds vcc 10% table 5.11 dc characteristics (9) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions permissible error of vcl pin external capacitance c vcl 3.3 4.7 6.1 f v r(vcc) vcc 1 / f r(vcc)
r01ds0257ej0200 rev.2.00 page 80 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics note: do not exceed the permissible total supply current. table 5.12 permissible output currents conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol max. unit permissible output low current ports 71 to 76, port 81, ports 90 to 95, port b5, port d3 i ol 10.0 ma riic pins 6.0 ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current total of all output pins i ol 110.0 total of ports 40 to 47, ports 50 to 55, ports 60 to 65 50.0 total of port 02, port e5, ports 10 and 11, ports 80 to 82 50.0 total of ports b4 to b7, ports d0 to d7, ports e0 and e1 55.0 total of ports 71 to 76 30.0 total of ports 90 to 95 30.0 permissible output high current ports 71 to 76, port 81, ports 9 0 to 95, port b5, port d3 i oh C 5.0 ports other than above normal output mode C 4.0 high-drive output mode C 8.0 permissible output high current total of all output pins i oh C 35.0 total of ports 40 to 47, ports 50 to 55, ports 60 to 65 C 25.0 table 5.13 output values of voltage conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. max. unit test conditions output low ports 71 to 76, port 81, ports 90 to 95, port b5, port d3 v ol 0.8vi ol = 10.0ma riic pins standard mode 0.4 i ol = 3.0ma fast mode 0.6 i ol = 6.0ma ports other than above normal output mode 0.8 i ol = 1.0ma high-drive output mode 0.8 i ol = 2.0ma output high ports 71 to 76, port 81, ports 90 to 95, port b5, port d3 v oh vcc C 0.8 vi oh = C 5.0ma ports 40 to 47, ports 50 to 55, ports 60 to 65 vref C 0.8 i oh = C 2.0ma ports other than above normal output mode vcc C 0.8 i oh = C 2.0ma high-drive output mode vcc C 0.8 i oh = C 4.0ma
r01ds0257ej0200 rev.2.00 page 81 of 133 apr 14, 2017 rx24t group 5. electri cal characteristics 5.2.1 normal i/o pin output characteristics (1) figure 5.6 to figure 5.9 show the characteristics when n ormal output is selected by the drive capacity control register. figure 5.6 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) figure 5.7 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v cc = 2.7 v v cc = 5.0 v v cc = 5.5 v v oh /v ol [v] i oh /i ol vs v oh /v ol 20 15 5 0 -5 -15 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i oh /i ol [ma] ta = 25c ta = 85c v oh /v ol [v] 10 -10 ta = 25c ta = - 40c ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 82 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.8 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.0 v when normal output is selected (reference data) figure 5.9 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 85c ta = 25c ta = -40c ta = 85c ta = -40c i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 85c ta = 25c ta = -40c ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 83 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.2.2 standard i/o pin outp ut characteristics (2) figure 5.10 to figure 5.13 show the characteristics when high-drive output is selected by the drive capacity control register. figure 5.10 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) figure 5.11 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v oh /v ol [v] 150 100 50 0 -50 -100 -150 i oh /i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v cc = 2.7 v v cc = 5.0 v v cc = 5.5 v i oh /i ol vs v oh /v ol 40 30 10 0 -10 -30 -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i oh /i ol [ma] ta = 25c ta = 85c v oh /v ol [v] 20 -20 ta = 25c ta = -40c ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 84 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.12 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.0 v when normal output is selected (reference data) figure 5.13 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 85c ta = 25c ta = -40c ta = 85c ta = -40c i oh /i ol vs v oh /v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 85c ta = 25c ta = -40c ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 85 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.2.3 standard i/o pin outp ut characteristics (3) figure 5.14 to figure 5.17 show the output characteristics of the large current ports. figure 5.14 v oh /v ol and i oh /i ol voltage characteristics of large current ports at t a = 25c (reference data) figure 5.15 v oh /v ol and i oh /i ol temperature characteristics of large current ports at vcc = 2. 7 v (reference data) i oh /i ol vs v oh /v ol 250 150 100 0 -100 -150 -250 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v cc = 2.7 v v cc = 5.0 v v cc = 5.5 v v oh /v ol [v] 200 50 -50 -200 i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i oh /i ol [ma] ta = 25c ta = 85c v oh /v ol [v] ta = 25c ta = -40c ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 86 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.16 v oh /v ol and i oh /i ol temperature characteristics of large current ports at vcc = 5. 0 v (reference data) figure 5.17 v oh /v ol and i oh /i ol temperature characteristics of large current ports at vcc = 5. 5 v (reference data) i oh /i ol vs v oh /v ol 250 150 100 0 -100 -150 -250 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 85c ta = 25c ta = -40c ta = 85c ta = -40c 200 50 -50 -200 i oh /i ol vs v oh /v ol 250 150 100 0 -100 -150 -250 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 85c ta = 25c ta = -40c ta = 85c ta = -40c 200 50 -50 -200
r01ds0257ej0200 rev.2.00 page 87 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.2.4 riic pin output characteristics figure 5.18 to figure 5.21 show the output characteristics of the riic pin. figure 5.18 v ol and i ol voltage characteristics of riic output pin at t a = 25c (reference data) figure 5.19 v ol and i ol temperature characteristics of r iic output pin at vcc = 2.7 v (reference data) i ol vs v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v ol [v] i ol vs v ol 40 30 10 0 -10 -30 -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i ol [ma] ta = 25c v ol [v] 20 -20 ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 88 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.20 v ol and i ol temperature characteristics of r iic output pin at vcc = 5.0 v (reference data) figure 5.21 v ol and i ol temperature characteristics of r iic output pin at vcc = 5.5 v (reference data) i ol vs v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i ol [ma] v ol [v] ta = 25c ta = 85c ta = -40c i ol vs v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i ol [ma] v ol [v] ta = 25c ta = 85c ta = -40c
r01ds0257ej0200 rev.2.00 page 89 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.3 ac characteristics 5.3.1 clock timing note 1. the lower-limit frequency o f fclk is 1 mhz during progra mming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non- integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. note 1. the lower-limit frequency o f fclk is 1 mhz during progra mming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non- integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. table 5.14 operating frequency value (high-speed operating mode) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit operating frequency system clock (iclk) f max 8 0m h z flashif clock (fclk)* 1, * 2 3 2 peripheral module clock (pclka) 80 peripheral module clock (pclkb) 40 peripheral module clock (pclkd) 40 table 5.15 operating frequency value (middle-speed operating mod e) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit operating frequency system clock (iclk) f max 1 2m h z flashif clock (fclk)* 1, * 2 1 2 peripheral module clock (pclka) 12 peripheral module clock (pclkb) 12 peripheral module clock (pclkd) 12
r01ds0257ej0200 rev.2.00 page 90 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note 1. time until the clock can be used after the main clock os cillator stop bit (mosccr.mostp) is set to 0 (operating) when t he external clock is stable. note 2. reference values when an 8-mhz resonator is used. when specifying the main clock o scillator stabilization time, s et the moscwtcr register with a stabilization time value that i s equal to or greater than the resonator-manufacturer-recommended value. after changing the setting of the mosccr.mostp bit so that the main clock oscillator operates, read the oscovfsr.moovf flag to confirm that is has become 1, and then start using the main clock. figure 5.22 extal external clock input timing table 5.16 clock timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions extal external clock input cycle time t xcyc 50 ns figure 5.22 extal external clock input high pulse width t xh 20 ns extal external clock input low pulse width t xl 20 ns extal external clock rise time t xr 5 ns extal external clock fall time t xf 5 ns extal external clock input wait time * 1 t xwt 0.5 s main clock oscillator oscillation frequency f main 120mhz main clock oscillation st abilization time (crystal) * 2 t mainosc 3 ms figure 5.23 main clock oscillation st abilization time (ceramic resonator) * 2 t mainosc 50s loco clock oscillation frequency f loco 3.44 4.0 4.56 mhz loco clock oscillati on stabilization time t loco 0.5 s figure 5.24 hoco clock oscillation frequency f hoco (32mhz) 31.52 32 32.48 mhz t a = C40 to C20c 31.68 32 32.32 mhz t a = C20 to +75c 31.52 32 32.48 mhz t a = +75 to +85c f hoco (64mhz) 63.04 64 64.96 mhz t a = C40 to C20c 63.36 64 64.64 mhz t a = C20 to +75c 63.04 64 64.96 mhz t a = +75 to +85c hoco clock oscillation stabilization time t hoco (32mhz) 37.1 s figure 5.26 t hoco (64mhz) 80.6 s figure 5.26 iwdt-dedicated clock oscillation frequency f iloco 12.75 15 17.25 khz iwdt-dedicated clock oscillation stabilization time t iloco 50 s figure 5.27 pll circuit oscillation frequency f pll 40 80 mhz pll clock oscillation stabilization time t pll 50 s figure 5.28 pll free-running oscillation frequency f pllfr 8mhz t xh t xcyc extal external clock input vcc 0.5 t xl t xr t xf
r01ds0257ej0200 rev.2.00 page 91 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.23 main clock os cillation start timing figure 5.24 loco clock oscillation start timing figure 5.25 hoco clock oscillatio n start timing ( after reset is canceled by setting ofs1.hocoen bit to 0) figure 5.26 hoco clock oscillatio n start timing (oscillation is started by setting hococr.hcstp bit) main clock oscillator output mosccr.mostp t mainosc loco clock oscillator output lococr.lcstp t loco res# internal reset hoco clock ofs1.hocoen t reswt hoco clock hococr.hcstp t hoco
r01ds0257ej0200 rev.2.00 page 92 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.27 iwdt-dedicated clo ck oscillation start timing figure 5.28 pll clock o scillation start timing (pll is operated after main clock osci llation has settled) iwdt-dedicated clock oscillator output ilococr.ilcstp t iloco pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output t pll
r01ds0257ej0200 rev.2.00 page 93 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.3.2 reset timing note 1. when iwdtcr.cks[3:0] = 0000b. figure 5.29 reset input timing at power-on figure 5.30 reset input timing (1) figure 5.31 reset input timing (2) table 5.17 reset timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions res# pulse width at power-on t reswp 3 ms figure 5.29 other than above t resw 30 s figure 5.30 wait time after res# cancellation (at power-on) t reswt 27.5 ms figure 5.29 wait time after res# cancellation (during powered-on state) t reswt 114 s figure 5.30 independent watchdog timer reset period t reswiw 1 iwdt clock cycle figure 5.31 software reset period t reswsw 1 iclk cycle wait time after independent watchdo g timer reset cancellation* 1 t resw2 300 s wait time after software reset cancellation t resw2 168 s vcc res# t reswp internal reset t reswt res# internal reset t reswt t resw independent watchdog timer reset software reset internal reset t reswt2 t reswiw, t reswsw
r01ds0257ej0200 rev.2.00 page 94 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note 1. the recovery time varies depending on the state of each oscillator when the wait instruc tion is executed. the recovery time when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as th e system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of crystal is 20 mhz. when the main clock oscillator w ait control register (moscwtcr) is set to 04h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. note 3. when the frequency of pll is 80 mhz. when the main clock oscillator w ait control register (moscwtcr) is set to 04h. when the frequencies of iclk and pclka are set to 80 mhz, pclkb and pclkd are set to 40 mhz, and fclk is set to 20 mhz. note 4. when the frequency of the external clock is 20 mhz. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. note 5. when the frequency of pll is 80 mhz. when the main clock oscillator w ait control register (moscwtcr) is set to 00h. when the frequencies of iclk and pclka are set to 80 mhz, pclkb and pclkd are set to 40 mhz, and fclk is set to 20 mhz. note 6. when the frequency of the high-speed on-chip oscillator is 32 mhz. when the high-speed on-chip oscillator wait control register (hocowtcr) is set to 05h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. note 7. when the frequency of the high-speed on-chip oscillator is 64 mhz. set the high-speed on- chip oscillator wait control r egister (hocowtcr) is set to 06h. when the frequencies of iclk and pclk a are set to 64 mhz, and the frequencies of pclkb, pclkd, and fclk are set to 32 mhz. note 8. when the frequency of the high-speed on-chip oscillator is 32 mhz, and the frequency of pll is 80 mhz. when the high-sp eed on-chip oscillator wait control register (hocowtcr) is set to 05h. when the frequencies of iclk and pclka are set to 80 mhz, the frequencies of pclkb and pclkd are set to 40 mhz, and the frequency of fclk is set to 20mhz. note 9. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. table 5.18 timing of recovery from low power consumption modes ( 1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 high-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc 2 3 ms figure 5.32 main clock oscillator and pll circuit operating* 3 t sbypc 2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex 3550s main clock oscillator and pll circuit operating* 5 t sbype 7095s hoco clock operation hoco clock oscillator operation 1* 6 t sbyho 4055s hoco clock oscillator operation 2* 7 7590s hoco clock oscillator, pll circuit operation* 8 t sbyph 110130s loco clock oscill ator operating* 9 t sbylo 4055s
r01ds0257ej0200 rev.2.00 page 95 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note 1. the recovery time varies depending on the state of each oscillator when the wait instruc tion is executed. the recovery time when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as th e system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of the crystal is 12 mhz. when the main clock oscillator w ait control register (moscwtcr) is set to 04h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. note 3. when the frequency of pll is 48 mhz. when the main clock oscillator w ait control register (moscwtcr) is set to 04h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are set to 12 mhz. note 4. when the frequency of the external clock is 12 mhz. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. note 5. when the frequency of pll is 48 mhz. when the main clock oscillator w ait control register (moscwtcr) is set to 00h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are set to 12 mhz. note 6. when the frequency of the high-speed on-chip oscillator is 32 mhz. when the high-speed on-chip oscillator wait control register (hocowtcr) is set to 05h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are set to 8 mhz. note 7. when the frequency of the high-speed on-chip oscillator is 64 mhz. set the high-speed on- chip oscillator wait control r egister (hocowtcr) is set to 06h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are set to 8 mhz. note 8. when the frequency of the high-speed on-chip oscillator is 32 mhz, and the frequency of pll is 80 mhz. when the high-sp eed on-chip oscillator wait control register (hocowtcr) is set to 0 5h. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are set to 10 mhz. note 9. when the frequencies of iclk, fclk, pclka, pclkb, and pclkd are not divided. table 5.19 timing of recovery from low power consumption modes ( 2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 middle-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc 2 3 ms figure 5.32 main clock oscillator and pll circuit operating* 3 t sbypc 2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex 3 4s main clock oscillator and pll circuit operating* 5 t sbype 6585s hoco clock oscillator operating hoco clock oscillator operating 1 * 6 t sbyho 4050s hoco clock oscillator operating 2 * 7 7585s hoco clock oscillator and pll circuit operating* 8 t sbyph 110 125 s loco clock oscill ator operating* 9 t sbylo 5 7s
r01ds0257ej0200 rev.2.00 page 96 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.32 software standby mode recovery timing note 1. oscillators continue oscillating in deep sleep mode. note 2. when the frequencies of iclk, fclk, pclka, pclkb, and pc lkd are 32 mhz. note 3. when the frequencies of iclk, fclk, pclka, pclkb, and pc lkd are 12 mhz. figure 5.33 deep sleep mode recovery timing note: values when the frequencies of pclka, pclkb, pclkd, and fc lk are not divided. table 5.20 timing of recovery from low power consumption modes ( 3) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions recovery time from deep sleep mode* 1 high-speed mode* 2 t dslp 2 3.5 s figure 5.33 middle-speed mode* 3 t dslp 3 4s table 5.21 operating mode transition time conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c mode before transition mode after transition iclk frequency transition time unit min. typ. max. high-speed operating mode middle-speed operating modes 8 mhz 10 s middle-speed operating modes high- speed operating mode 8 mhz 37.5 s oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbyho, t sbyph, t sbylo oscillator iclk irq deep sleep mode t dslp
r01ds0257ej0200 rev.2.00 page 97 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.3.4 control signal timing note: 200 ns minimum in software standby mode. note 1. t pcyc indicates the cycle of pclkb. note 2. t nmick indicates the cycle of the nmi digital filter sampling clock. note 3. t irqck indicates the cycle of the irqi digital filter sampling clock (i = 0 to 7). figure 5.34 nmi interrupt input timing figure 5.35 irq interrupt input timing table 5.22 control signal timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ns nmi digital filter disabled (nmiflte.nflten = 0) t pcyc 2 200 ns t pcyc 2* 1 t pcyc 2 > 200 ns 200 nmi digital filter enabled (nmiflte.nflten = 1) t nmick 3 200 ns t nmick 3.5* 2 t nmick 3 > 200 ns irq pulse width t irqw 200 ns irq digital filter disabled (irqflte0.flteni = 0) t pcyc 2 200 ns t pcyc 2* 1 t pcyc 2 > 200 ns 200 irq digital filter enabled (irqflte0.flteni = 1) t irqck 3 200 ns t irqck 3.5* 3 t irqck 3 > 200 ns nmi t nmiw irq t irqw
r01ds0257ej0200 rev.2.00 page 98 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.3.5 timing of on-ch ip peripheral modules note 1. t pcyc : pclk cycle, t pacyc : pclka cycle note 2. t cac : cac count clock source cycle table 5.23 timing of on-chip peripheral modules (1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. max. unit *1 test conditions i/o ports input data pulse width t prw 1.5 t pcyc figure 5.36 mtu3 input capture input pulse width single-edge setting t ticw 3t pacyc figure 5.37 both-edge setting 5 timer clock pulse width single-edge setting t tckwh , t tckwl 3t pacyc figure 5.38 both-edge setting 5 phase counting mode 5 poe3 poe# input pulse width t poew 1.5 t pcyc figure 5.39 gpt input capture input pulse width single-edge setting t gticw 1.5 t pacyc figure 5.40 both-edge setting 2.5 external trigger input pulse width single-edge setting t gtetw 1.5 t pacyc figure 5.41 both-edge setting 2.5 timer clock pulse width t gtckwh 1.5 t pacyc figure 5.42 t gtckwl tmr timer clock pulse width single-edge setting t tmcwh , t tmcwl 1.5 t pcyc figure 5.43 both-edge setting 2.5 sci input clock cycle asynchronous t scyc 4t pcyc figure 5.44 clock synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr 20ns input clock fall time t sckf 20ns output clock cycle asynchronous t scyc 16 t pcyc figure 5.45 clock synchronous 4 output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr 20ns output clock fall time t sckf 20ns transmit data delay time (master) clock synchronous t txd 40ns transmit data delay time (slave) clock synchronous vcc = 4.0 v or above 40 ns vcc = 2.7 v or above 65 ns receive data setup time (master) clock synchronous vcc = 4.0 v or above t rxs 40 ns vcc = 2.7 v or above 65 ns receive data setup time (slave) clock synchronous 40 ns receive data hold time clock synchronous t rxh 40 ns a/d converter trigger input pulse width t trgw 1.5 t pcyc figure 5.46 cac cacref input pulse width t pcyc t cac *2 t cacref 4.5 t cac + 3 t pcyc ns t pcyc > t cac *2 5 t cac + 6.5 t pcyc
r01ds0257ej0200 rev.2.00 page 99 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. n: an integer from 1 to 8 that can be set by the rspi cl ock delay register (spckd) note 3. n: an integer from 1 to 8 that can be set by the rspi sl ave select negation delay register (sslnd) table 5.24 timing of on-chip peripheral modules (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 =avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c, c = 30pf item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc figure 5.47 slave 6 rspck clock high pulse width master vcc = 4.0 v or above t spckwh (t spcyc C t spckr C t spckf )/2 C 5 ns vcc = 2.7 v or above (t spcyc C t spckr C t spckf )/2 C 8 slave (t spcyc C t spckr C t spckf )/2 rspck clock low pulse width master vcc = 4.0 v or above t spckwl (t spcyc C t spckr C t spckf )/2 C 5 ns vcc = 2.7 v or above (t spcyc C t spckr C t spckf )/2 C 8 slave (t spcyc C t spckr C t spckf )/2 rspck clock rise/fall time output vcc = 4.0 v or above t spckr , t spckf 6n s vcc = 2.7 v or above 10 input 0.1 s/v data input setup time master vcc = 4.0 v or above t su 10 ns figure 5.48 to figure 5.51 vcc = 2.7 v or above 26 slave 20 data input hold time master rspck set to a division ratio other than pclkb divided by 2 t h t pcyc ns rspck set to pclkb divided by 2 t hf 0 slave t h 0 ssl setup time master t lead C30 + n* 2 t spcyc ns slave 6 t pcyc ssl hold time master t lag C30 + n* 3 t spcyc ns slave 6 t pcyc data output delay time master vcc = 4.0 v or above t od 1 0n s vcc = 2.7 v or above 14 slave 65 data output hold time master t oh 0n s slave 0 successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 6 t pcyc mosi and miso rise/fall time output t dr, t df 1 0n s input 1 s ssl rise/fall time output t sslr , t sslf 1 0n s input 1 s slave access time t sa 6t pcyc figure 5.50, figure 5.51 slave output release time t rel 5t pcyc
r01ds0257ej0200 rev.2.00 page 100 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note 1. t pcyc : pclk cycle table 5.25 timing of on-chip peripheral modules (3) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c, c = 30pf item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 5.47 sck clock cycle input (slave) 6 t pcyc sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr , t spckf 20ns data input setup time (master) vcc = 4.0 v or above t su 40 ns figure 5.48, figure 5.49 vcc = 2.7 v or above 65 data input setup time (slave) 40 data input hold time t h 40 ns ss input setup time t lead 3t spcyc ss input hold time t lag 3t spcyc data output delay time (master) t od 40ns data output delay time (slave) vcc = 4.0 v or above 40 vcc = 2.7 v or above 65 data output hold time master t oh C10 ns slave C10 data rise/fall time t dr , t df 20ns ss input rise/fall time t sslr , t sslf 20ns slave access time t sa 6t pcyc figure 5.50, figure 5.51 slave output release time t rel 6t pcyc
r01ds0257ej0200 rev.2.00 page 101 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note 1. t iiccyc : riic internal reference count clock (iic) cycle note 2. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the icfer.nfe bit = 1. table 5.26 timing of on-chip peripheral modules (4) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min.* 1, * 2 max. unit test conditions riic (standard mode, smbus) scl cycle time t scl 6 (12) t iiccyc + 1300 ns figure 5.52 scl high pulse width t sclh 3 (6) t iiccyc + 300 ns scl low pulse width t scll 3 (6) t iiccyc + 300 ns scl, sda rise time t sr 1000 ns scl, sda fall time t sf 300 ns scl, sda spike pulse removal time t sp 0 1 (4) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ns start condition hold time t stah t iiccyc + 300 ns repeated start condition setup time t stas 1000 ns stop condition setup time t stos 1000 ns data setup time t sdas t iiccyc + 50 ns data hold time t sdah 0n s scl, sda capacitive load c b 400 pf riic (fast mode) scl cycle time t scl 6 (12) t iiccyc + 600 ns figure 5.52 scl high pulse width t sclh 3 (6) t iiccyc + 300 ns scl low pulse width t scll 3 (6) t iiccyc + 300 ns scl, sda rise time t sr 300 ns scl, sda fall time t sf 300 ns scl, sda spike pulse removal time t sp 0 1 (4) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ns start condition hold time t stah t iiccyc + 300 ns repeated start condition setup time t stas 300 ns stop condition setup time t stos 300 ns data setup time t sdas t iiccyc + 50 ns data hold time t sdah 0n s scl, sda capacitive load c b 400 pf
r01ds0257ej0200 rev.2.00 page 102 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note 1. t pcyc : pclkb cycle note 2. c b is the total capacitance of the bus lines. figure 5.36 i/o port input timing figure 5.37 mtu3 input/output timing table 5.27 timing of on-chip peripheral modules (5) conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = a vcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min.* 2 max. unit test conditions simple i 2 c (standard mode) sda rise time t sr 1000 ns figure 5.52 sda fall time t sf 300 ns sda spike pulse removal time t sp 0 4 t pcyc * 1 ns data setup time t sdas 250 ns data hold time t sdah 0n s scl, sda capacitive load c b 400 pf simple i 2 c (fast mode) sda rise time t sr 300 ns figure 5.52 sda fall time t sf 300 ns sda spike pulse removal time t sp 0 4 t pcyc * 1 ns data setup time t sdas 100 ns data hold time t sdah 0n s scl, sda capacitive load c b 400 pf port pclk t prw output compare output input capture input pclka t ticw
r01ds0257ej0200 rev.2.00 page 103 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.38 mtu3 clock input timing figure 5.39 poe# input timing figure 5.40 input timing of gpt input capture figure 5.41 timing of the g pt external trigger input mtclka to mtclkd pclka t tckwl t tckwh poen# input pclk t poew input capture input pclka t gticw external trigger pclka t gtetw
r01ds0257ej0200 rev.2.00 page 104 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.42 gpt clock input timing figure 5.43 tmr clock input timing figure 5.44 sck clock input timing gteclka to gteclkd pclka t gtckwl t gtckwh pclk tmci0 to tmci7 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn n = 1, 5, 6
r01ds0257ej0200 rev.2.00 page 105 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.45 sci input/output timing: clock synchronous mode figure 5.46 a/d converter external trigger input timing t txd t rxs t rxh txdn rxdn sckn n = 1, 5, 6 pclk t trgw adtrg0# to adtrg2#
r01ds0257ej0200 rev.2.00 page 106 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.47 rspi clock timing a nd simple spi clock timing figure 5.48 rspi timing (master, cpha = 0) and simple spi clock timing (master, ckph = 1) t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc n = 1, 5, 6 sckn master select output sckn slave select input rspcka master select output rspcka slave select input simple spi rspi t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output n = 1, 5, 6 simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output
r01ds0257ej0200 rev.2.00 page 107 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.49 rspi timing (master, cpha = 1) and simple spi clock timing (master, ckph = 0) figure 5.50 rspi timing (slave, cpha = 0) and simple spi clock t iming (slave, ckph = 1) ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od n = 1, 5, 6 t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input n = 1, 5, 6 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input
r01ds0257ej0200 rev.2.00 page 108 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.51 rspi timing (slave, cpha = 1) and simple spi clock t iming (slave, ckph = 0) figure 5.52 riic bus interface inp ut/output timing and simple i 2 c bus interface input/output timing t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input n = 1, 5, 6 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input test conditions v ih = vcc 0.7, v il = vcc 0.3 sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respecti vely. s: start condition p: stop condition sr: repeated start condition
r01ds0257ej0200 rev.2.00 page 109 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.4 a/d conversion characteristics note: the characteristics apply when no pin functions other than a/d converter input are used . absolute accuracy includes quantization errors. offset error, full-scale error, dnl differ ential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is t he sum of the sampling time and the comparison time. as the te st conditions, the number of samp ling states is indicated. table 5.28 a/d conversion characteristics (1) conditions: vcc = 4.5 v to 5.5 v, avcc0 = av cc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item min. typ. max. unit test conditions frequency 1 40 mhz resolution 12 bit conversion time* 1 (operation at pclkd = 40 mhz) permissible signal source impedance (max.) = 1.0 k sample-and-hold circuit not in use 1.00 s high-precision channel adsstrn.sst[7:0] bits = 08h 1.25 s normal-precision channel adsstrn.sst[7:0] bits = 12h permissible signal source impedance (max.) = 1.0 k sample-and-hold circuit in use 1.65 s high-precision channel adsstrn.sst[7:0] bits = 08h adshcr.sstsh[7:0] bits = 0dh an100 to 102 = 0.25 v to avcc1 C 0.25 v analog input capacitance 12 pf offset error 2.0 6.5 lsb full-scale error 2.0 6.5 lsb quantization error 0.5 lsb absolute accuracy sample-and-hold circuit in use 2.5 8.0 lsb an100 to 102 = 0.25v to avcc1 C 0.25 sample-and-hold circuit not in use 3.0 8.0 lsb dnl differential nonlinearity error 0.5 1.5 lsb inl integral nonlinearity error 1.5 4.0 lsb
r01ds0257ej0200 rev.2.00 page 110 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used . absolute accuracy includes quantization errors. offset error, full-scale error, dnl differ ential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note 1. the conversion time is t he sum of the sampling time and the comparison time. as the te st conditions, the number of samp ling states is indicated. note 1. the a/d internal reference voltage indicates the voltage when the internal reference voltage is input to the a/d conver ter. table 5.29 a/d conversion characteristics (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = av cc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item min. typ. max. unit test conditions frequency 1 40 mhz resolution 12 bit conversion time* 1 (operation at pclkd = 40 mhz) permissible signal source impedance (max.) = 1.0 k sample-and-hold circuit not in use 1.15 s high-precision channel adsstrn.sst[7:0] bits = 0eh 1.30 s normal-precision channel adsstrn.sst[7:0] bits = 14h permissible signal source impedance (max.) = 1.0 k sample-and-hold circuit in use 1.90 s high-precision channel adsstrn.sst[7:0] bits = 0eh adshcr.sstsh[7:0] bits = 11h an100 to 102 = 0.25 v to avcc1 C 0.25 v analog input capacitance 12 pf offset error 2.0 6.5 lsb full-scale error 2.0 6.5 lsb quantization error 0.5 lsb absolute accuracy 3.0 8.0 lsb dnl differential nonlinearity error 0.5 1.5 lsb inl integral nonlinearity error 1.5 4.0 lsb table 5.30 a/d converter channel classification classification channel conditions remarks high-precision channel an000 to an003 , an100 to an103 , an200 to an211 avcc0 = avcc1 = avcc2= vref = 2.7 to 5.5v normal-precision channel an016, an116 vcc = avcc0 = avcc1 =avcc2 = vref = 2.7 to 5.5v internal reference voltage input channel internal reference voltage avcc0 = avcc1 = avcc2= vref = 2.7 to 5.5v table 5.31 a/d internal refer ence voltage characteristics conditions: vcc = 2.7 v to 5.5v, avcc0 = avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item min. typ. max. unit test conditions internal reference voltage input channel* 1 1.35 1.43 1.50 v
r01ds0257ej0200 rev.2.00 page 111 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.53 illustrat ion of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based o n the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measurin g absolute accuracy, the voltage at the midpoi nt of the width of analog input voltage (1-lsb width), th at can meet the expectation of o utputting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolu tion is used and if reference voltage (avccn (n = 0 to 2)) is 3.072 v, then 1-lsb width becom es 0.75 mv, and 0 mv, 0.75 mv, 1.5 mv, ... are used as analog input voltages. if analog input voltage is 6 mv, absolute accuracy = 5 lsb mea ns that the actual a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expected fr om the theoretical a/d conversion characteristics. integral nonlinea rity error (inl) integral nonlinearity error is the maximum deviation between th e ideal line when the measur ed offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic avccn (n = 0 to 2) (full-scale) a/d converter output code
r01ds0257ej0200 rev.2.00 page 112 of 133 apr 14, 2017 rx24t group 5. electrical characteristics differential nonlinearity error (dnl) differential nonlinear ity error is the difference between 1-lsb width based on the ideal a/d conversion ch aracteristics and the width of the actual output code. offset error offset error is the difference between a t ransition point of th e ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point o f the ideal last output code and the actual last output code.
r01ds0257ej0200 rev.2.00 page 113 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.5 programmable gain amp lifier characteristics table 5.32 programmable gain amplifier characteristics conditions: vcc = 2.7 v to avcc0, avcc0 = avcc1 = avcc2 = vref = 4.5 v to 5.5 v, vss = avss 0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions input offset voltage v poff 8mv input voltage range v pin v pout (min)/g v pout (max)/g v output voltage range v pout 0.1 avcc 0.9 avcc v gain g 2.000 4.444 gain error g err 1.0 2.0 % g = 2.000, 2.500, 3.077 1.5 3.0 % g = 3.636, 4.000, 4.444 slew rate sr 10 v/s operation stabiliz ation wait time t start 5.0s
r01ds0257ej0200 rev.2.00 page 114 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.6 comparator characteristics figure 5.54 comparator response time table 5.33 comparator characteristics conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions offset voltage v cioff 40mv reference input voltage range v cref 0 vref v response time t cr 200 ns vod = 100 mv cmpctl.cdfs = 0 t cf 200 ns stabilization wait time for input selection t cwait 300 ns operation stabiliz ation wait time t cmp 1s reference input voltage cmpc00, cmpc02, cmpc10, cmpc12, cmpc20, cmpc22, cmpc30, cmpc32 comp0 to comp3 100 mv 100 mv t cr t cf
r01ds0257ej0200 rev.2.00 page 115 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.7 d/a conversion characteristics note: when using ports 23 and 24 as da0 and da1 outputs, make su re that vcc da output voltage. table 5.34 characteristics of d /a conversion (chip version a) conditions: vcc = 2.7 v to 5.5 v, avcc0 = av cc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions resolution 8 bit conversion time t dconv 3 . 0 s absolute accuracy 3.0 lsb table 5.35 characteristics of d /a conversion (chip version b) conditions: vcc = 2.7 v to 5.5 v, avcc0 = av cc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions resolution 8 bit conversion time t dconv 3 . 0 s absolute accuracy 3.0 lsb output load resistance 4 m output load capacity 35 pf output resistance 9.0 k
r01ds0257ej0200 rev.2.00 page 116 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.8 power-on reset circuit and vo ltage detection circuit charact eristics note: these characteristics appl y when noise is not superimposed on the power supply. when a setting is made so that the voltag e detection level overlaps with t hat of the voltage detection cir cuit (lvd2), it cannot be specifi ed which of lvd1 and lvd2 is u sed for voltage detection. note 1. n in the symbol v det0_n denotes the value of the lvds0[1:0] bits. note 2. n in the symbol v det1_n denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note 3. n in the symbol v det2_n denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. table 5.36 power-on reset circuit and voltage detection circuit characteristics (1) conditions: vcc = 0 v to 5.5 v, avc c0 = avcc1 = avcc2 = vref = v cc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, t a = C40 to +85c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 1.35 1.50 1.65 v figure 5.55, figure 5.56 voltage detection circuit (lvd0)* 1 v det0_0 3.67 3.84 3.97 v v det0_1 2.70 2.82 3.00 v det0_2 2.37 2.51 2.67 voltage detection circuit (lvd1)* 2 v det1_0 4.12 4.29 4.42 v figure 5.58 at falling edge vcc v det1_1 3.98 4.14 4.28 v det1_2 3.86 4.02 4.16 v det1_3 3.68 3.84 3.98 v det1_4 2.99 3.10 3.29 v det1_5 2.89 3.00 3.19 v det1_6 2.79 2.90 3.09 v det1_7 2.68 2.79 2.98 v det1_8 2.57 2.68 2.87 voltage detection circuit (lvd2)* 3 v det2_0 4.08 4.29 4.48 figure 5.59 at falling edge vcc v det2_1 3.95 4.14 4.35 v det2_2 3.82 4.02 4.22 v det2_3 3.62 3.84 4.02 table 5.37 power-on reset circuit and voltage detection circuit characteristics (2) conditions: vcc = 0 v to 5.5 v, avc c0 = avcc1 = avcc2 = vref = v cc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, ta = C40 to +85c item symbol min. typ. max. unit test conditions wait time after power-on reset cancellation at normal startup t por D 28.4 D ms figure 5.56 wait time after voltage monitoring 0 reset cancellation t lvd0 D 568 D s figure 5.57 wait time after voltage monitoring 1 reset cancellation t lvd1 D 100 D s figure 5.58 wait time after voltage monitoring 2 reset cancellation t lvd2 D 100 D s figure 5.59 response delay time t det D D 350 s figure 5.55 minimum vcc down time* 1 t voff 350 D D s figure 5.55, vcc = 1.0 v or above power-on reset enable time t w(por) 1 D D ms figure 5.56, vcc = below 1.0 v lvd operation stabilizati on time (after lvd is enabled) td (e-a) D D 300 s figure 5.58, figure 5.59 hysteresis width (lvd0, lvd1 and lvd2) v lvh D 70 D mv vdet1_0 to 4 selected D 60 D vdet0_0 to 2 selected vdet1_5 to 8 selected lvd2 selected
r01ds0257ej0200 rev.2.00 page 117 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note: these characteristics appl y when noise is not superimposed on the power supply. when a setting is made so that the voltag e detection level overlaps with t hat of the voltage detection cir cuit (lvd1), it cannot be specifi ed which of lvd1 and lvd2 is u sed for voltage detection. note 1. the minimum vcc down time indicates the time when vcc is below the minimum value of voltage detection levels v por , v det0 , v det1 , and v det2 for the por/lvd. figure 5.55 voltage d etection reset timing figure 5.56 power-on reset timing figure 5.57 voltage detection circuit timing (vdet0) internal reset signal (active-low) vcc t voff t por t det v por t det 1.0 v internal reset signal (active-low) vcc t por v por 1.0 v t w(por) *1 t det note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (1.0 v). when vcc turns on, maintain t w(por) for 1.0 ms or more. t voff v det0 vcc t det t det internal reset signal (active-low) v lvh t lvd0
r01ds0257ej0200 rev.2.00 page 118 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.58 voltage detection circuit timing (v det1 ) figure 5.59 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0257ej0200 rev.2.00 page 119 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.9 oscillation stop detection timing figure 5.60 oscillation stop detection timing table 5.38 oscillation stop detection timing conditions: vcc = 2.7 v to 5.5 v, avcc0 =avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, ta = C40 to +85c item symbol min. typ. max. unit test conditions detection time t dr 1 ms figure 5.60 t dr main clock ostdsr.ostdf low-speed clock iclk t dr main clock ostdsr.ostdf iclk when the main clock is selected when the pll clock is selected pll clock
r01ds0257ej0200 rev.2.00 page 120 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.10 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprog ram/ erase cycle is n times (n = 1000), erasing can be performed n t imes for each block. for instance, when 4-byte programming is performed 256 times for different addresses in 1-kbyte block an d then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for sever al times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when using the flash memory programmer an d the self-programming library provided from renesas electronic s. note 3. this result is obtai ned from reliability testing. note: does not include the time until each operation of the flas h memory is started after instructions are executed by software . note: the lower-limit frequency of f clk is 1 mhz during programm ing or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non -integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.39 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 1000 times data hold time after 1000 times of n pec t drp 20* 2, * 3 year t a = +85c table 5.40 rom (flash memory for code storage) characteristics ( 2): high-speed o perating mode conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v temperature range for the pr ogramming/erasure operation: t a = C40 to +85c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 8-byte t p8 112.0 967.0 52.3 490.5 s erasure time 2-kbyte t e2k 8.7 278.1 5.5 214.6 ms 256-kbyte (when block erase command used) t e256k 469.1 9813.6 41.2 1049.2 ms 256-kbyte (when all- block erase command used) t ea256k 463.9 9609.0 36.0 839.5 ms 512-kbyte (when block erase command used) t e512k 927.8 19218.0 72.0 1678.9 ms 512-kbyte (when all- block erase command used) t ea512k 922.7 19013.4 66.7 1469.2 ms blank check time 8-byte t bc8 55.0 16.1 s 2-kbyte t bc2k 1840.0 135.7 s erase operation forcible stop time t sed 18.0 10.7 s start-up area switching setting time t sas 12.3 566.5 6.2 433.5 ms access window time t aws 12.3 566.5 6.2 433.5 ms rom mode transition wait time 1 t dis 2.0 2.0 s rom mode transition wait time 2 t ms 5.0 5.0 s
r01ds0257ej0200 rev.2.00 page 121 of 133 apr 14, 2017 rx24t group 5. electrical characteristics note: does not include the time until each operation of the flas h memory is started after instructions are executed by software . note: the lower-limit frequency of f clk is 1 mhz during programm ing or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non -integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.41 rom (flash memory for code storage) characteristics ( 3): middle-speed operating mode conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v temperature range for the pr ogramming/erasure operation: t a = C40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 8-byte t p8 152.0 1367.0 97.9 936.0 s erasure time 2-kbyte t e2k 8.8 279.7 5.9 220.8 ms 256-kbyte (when block erase command used) t e256k 469.2 9816.9 100.5 2260.1 ms 256-kbyte (when all- block erase command used) t ea256k 464.0 9610.7 95.3 2053.7 ms 512-kbyte (when block erase command used) t e512k 928.0 19221.2 190.6 4107.3 ms 512-kbyte (when all- block erase command used) t ea512k 922.7 19015.0 185.4 3901.0 ms blank check time 8-byte t bc8 85.0 50.9 s 2-kbyte t bc2k 1870.0 401.5 s erase operation forcible stop time t sed 28.0 21.3 s start-up area switching setting time t sas 13.0 573.3 7.7 450.1 ms access window time t aws 13.0 573.3 7.7 450.1 ms rom mode transition wait time 1 t dis 2.0 2.0 s rom mode transition wait time 2 t ms 3.0 3.0 s
r01ds0257ej0200 rev.2.00 page 122 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.11 e2 dataflash characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprog ram/ erase cycle is n times (n = 100000), erasing can be performed n times for each block . for instance, when 1-byte programming is performed 1000 times for different addresses in 1-kbyte bloc k and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when using the flash memory programmer an d the self-programming library provided from renesas electronic s. note 3. this result is obtai ned from reliability testing. note: does not include the time until each operation of the flas h memory is started after instructions are executed by software . note: the lower-limit frequency of f clk is 1 mhz during programm ing or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non -integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. note: does not include the time until each operation of the flas h memory is started after instructions are executed by software . note: the lower-limit frequency of f clk is 1 mhz during programm ing or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non -integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.42 e2 dataflash characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n dpec 100000 1000000 times data hold time after 10000 times of n dpec t ddrp 20* 2, * 3 year t a = +85c after 100000 times of n dpec 5* 2, * 3 year after 1000000 times of n dpec 1 * 2, * 3 year t a = +25c table 5.43 e2 dataflash character istics (2): high-s peed operatin g mode conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, temperature range for the pr ogramming/erasure operation: t a = C40 to +85c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 1-byte t dp1 95.0 797.0 40.8 375.5 s erasure time 1-kbyte t de1k 19.5 498.5 6.2 229.4 ms 8-kbyte t de8k 119.8 2555.7 12.9 367.2 ms blank check time 1-byte t dbc1 55.0 16.1 s 1-kbyte t dbc1k 7216.0 495.7 s erase operation forcible stop time t dsed 16.0 10.7 s data flash-module stop release time t dstop 5.0 5.0 s table 5.44 e2 dataflash character istics (3): middle -speed operat ing mode conditions: vcc = 2.7 v to 5.5 v, avcc0 = avcc1 = avcc2 = vref = vcc to 5.5 v, vss = avss0 = avss1 = avss2 = 0 v, temperature range for the pr ogramming/erasure operation: t a = C40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 1-byte t dp1 135.0 1197.0 86.5 822.5 s erasure time 1-kbyte t de1k 19.6 500.1 8.0 264.1 ms 8-kbyte t de8k 119.9 2557.4 27.7 668.2 ms blank check time 1-byte t dbc1 85.0 50.9 s 1-kbyte t dbc1k 7246.0 1457.5 s erase operation forcible stop time t dsed 28.0 21.3 s data flash-module stop release time t dstop 0.72 0.72 s
r01ds0257ej0200 rev.2.00 page 123 of 133 apr 14, 2017 rx24t group 5. electrical characteristics 5.12 usage notes 5.12.1 connecting vcl capacitor and bypass capacitors this mcu integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the internal mcu to adjust automati cally to the optim um level. a 4. 7-f capacitor needs to be connected between this internal voltage-down power su pply (vcl pin) and vss pin. figure 5.61 to figure 5.63 shows how to connect external capacitors. place an external capacitor close to the p ins. do not apply the power supply voltage to the vcl pin. insert a multilayer ceramic cap acitor as a bypass capacitor bet ween each pair of t he power supply pi ns. implement a bypass capacitor to the mcu power supply pins as close as possi ble. use a recommended va lue of 0.1 f as the capacitance of the capacitors. fo r the capacitors related to cr ystal oscillation, see section 9, clock generation circuit in the users manual: hardware . for the capacitors related to analog modules, also see section 31, 12-bit a/d converter (s12adf) in the users manual: hardware . for notes on designing the printe d circuit board, see the descr iptions of the application note hardware design guide (r01an1411ej). the latest version can be downloaded from renesa s electronics website. figure 5.61 connecting capacitors (100 pins) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 vss vcc vss vcc vss vcc vss vcl vss vcc rx24t group plqp0100kb-b (100-pin lfqfp) (top view) bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f note: do not apply the power supply voltage to the vcl pin. use a 4.7-f multilayer ceramic for the vcl pin and place it cl ose to the pin. a recommended value is shown for the capacitance of the bypass capacitors.
r01ds0257ej0200 rev.2.00 page 124 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.62 connecting capacitors (80 pins) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 vss vcc vss vcc vss vcc vss vcl vss vcc rx24t group plqp0080ja-a (80-pin lqfp) plqp0080kb-b (80-pin lfqfp) (top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f note: do not apply the power supply voltage to the vcl pin. use a 4.7-f multilayer ceramic for the vcl pin and place it cl ose to the pin. a recommended value is shown for the capacitance of the bypass capacitors.
r01ds0257ej0200 rev.2.00 page 125 of 133 apr 14, 2017 rx24t group 5. electrical characteristics figure 5.63 connecting capacitors (64 pins) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx24t group plqp0064kb-c (64-pin lfqfp) (top view) vss vcc vss vcc vcl vss vcc external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f note: do not apply the power supply voltage to the vcl pin . use a 4.7-f multilayer ceramic for the vcl pin and place it cl ose to the pin . a recommended value is shown for the capacitance of the bypass capacitors .
r01ds0257ej0200 rev.2.00 page 126 of 133 apr 14, 2017 rx24t group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in packages on renesas electronics corporation website. figure a 100-pin lfqfp (plqp0100kb-b) mass (typ) [g] 0.6 unit: mm previous code renesas code plqp0100kb-b ? jeita package code p-lfqfp100-14x14-0.50 d e a 2 h d h e a a 1 b p c e x y l p l 1 13.9 13.9 15.8 15.8 0.05 0.15 0.09 0 0.45 min nom dimensions in millimeters reference symbol max 14.0 14.0 1.4 16.0 16.0 0.20 3.5 0.5 0.6 1.0 14.1 14.1 16.2 16.2 1.7 0.15 0.27 0.20 8 0.08 0.08 0.75 note) 1. dimensions ?*1? and ?*2? do not include mold flash. 2. dimension ?*3? does not include trim offset. 3. pin 1 visual index feature may vary, but must be located within the hatched area. 4. chamfers at corners are optional, size may vary. h d a 2 a 1 l p l 1 detail f a c 0.25 d 75 76 100 26 25 1 50 51 f note 4 note 3 index area *1 h e e *2 *3 b p e ys s m
r01ds0257ej0200 rev.2.00 page 127 of 133 apr 14, 2017 rx24t group appendix 1. package dimensions figure b 80-pin lqfp (plqp0080ja-a) l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.65 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.27 0.32 0.37 0.09 0.145 0.20 0.13 0.825 0.825 0.30 0.125 1.0 p-lqfp80-14x14-0.65 0.6g mass[typ.] fp-80w / fp-80wv plqp0080ja-a renesas code jeita package code previous code include trim offset. dimension " *3" does not note) do not include mold flash. dimensions " *1" and "*2" 1. 2. c 1 c b p b 1 terminal cross section a 2 c l a 1 a l 1 detail f z e z d h e h d d e *2 *1 *3 f 80 61 60 41 40 21 20 1 index mark e b p m s ys
r01ds0257ej0200 rev.2.00 page 128 of 133 apr 14, 2017 rx24t group appendix 1. package dimensions figure c 80-pin lfqfp (plqp0080kb-b)
r01ds0257ej0200 rev.2.00 page 129 of 133 apr 14, 2017 rx24t group appendix 1. package dimensions figure d 64-pin lfqfp (plqp0064kb-c)
r01ds0257ej0200 rev.2.00 page 130 of 133 apr 14, 2017 rx24t group revision history classifications - items with technical update document numb er: changes accordin g to the corresponding issued technical update - items without technical update document number: minor changes that do not require tech nical update to be issued revision history rx 24t group datasheet rev. date description classification page summary 1.00 nov 30, 2015 first edition, issued 2.00 apr 14, 2017 all chip version b, added the name of the previous produc t, changed to chip version a acc ording to the above the specification of the hoco, added the 64-pin package, added the specification of the voltag e detection 0 level select bit, changed tn-rx*-a171a/e 5. electrical characteristics the characteristics of hoco-/gpt-/rscan-related and chip versi on b, added 72 table 5.3 dc characteristics (1): ports 36 and 37, added 78 table 5.8 dc characteristics (6), changed 100 table 5.25 timing of on-chip peripheral modules (3), changed tn-rx*-a170a/e 115 table 5.34 characteristics o f d/a conversion (chip version a ), changed tn-rx*-a170a/e 125 figure 5.63 connecting capacitors (64 pins), added appendix 1. package dimensions 126 figure a 100-pin lfqfp (plqp0100kb-b), package part number, changed 128 figure c 80-pin lfqfp (plqp0080kb-b), package part number, c hanged 129 figure d 64-pin lfqfp (plqp0064kb-c), added all trademarks and registered tra demarks are the property of th eir respective owners. revision history
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
general precautions in the handling of microprocessing unit and microcontroller unit products the following usage notes are applicable to all microprocessing unit and microcontroller unit products from renesas. for detailed usage notes on the products cov ered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accordance with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high - impedance state. in operation with an unused pin in the open - circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot - through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power - on the state of the prod uct is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on - chip power - on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of microprocessing unit or microcontroller unit products in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system - evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. renesas electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics hereby expressly disclaims any warranties against and liability for infringement or any other disputes i nvolving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of renesas electronics products or technical information described in this document, including but not lim ited to, the product data, drawing, chart, program, algorithm, application examples. 3. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property ri ghts of renesas electronics or others. 4. you shall not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas elec tronics products. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he intended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale com munication equipment; key financial terminal systems; safety control equipment; etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (space and undersea repeaters; nuclear power control systems; aircra ft control systems; key plant systems; military equipment; etc.). renesas electronics disclaims any and all liability for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. when using the renesas electronics products, refer to the latest product information (data sheets, user?s manuals, applicati on notes, "general notes for handling and using semiconductor devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by renesas electronics with respect to maximum ratings, operating power supply voltage range, heat radiation characteristics, installation, etc. renesas electronics disclaims any and all liability for any malfunctions or failure or acci dent arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of renesas electronics products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please ensure to implement safety measures to guard them against the possibility of bodily injury, injury or damage caused by fire, and social damage in the event of failure or malfunction of renesas electronics products, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures by your own responsibility as warranty for your products/system. because the evaluation of microcomputer software alone is very difficult and not practical, please e valuate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please investigate applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive carefully and sufficiently and use renesas electronics products in compliance with all these applicable laws and regulations. renesas electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technologies shall not be used for or incorporated into any products or systems whose manuf acture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you shall not use renesas electronics products or technologies for (1) any purpose relating to the development, design, manufacture, use, stockpiling, etc., of weapons of mass destruction, such as nuclear weapons, chemical weapons, or biological weapons, or missiles (including unmanned aerial vehicles (uavs)) for d elivering such weapons, (2) any purpose relating to the development, design, manufacture, or use of conventional weapons, or (3) any other purpose of disturbing international peace and security, and you shall not sell, export, lease, transfer, or release renesas electronics products or technologies to any third party whether directly or indirectly with knowledge or reason to know that the third party or any other party will engage in the activities described above. when exporting, selling, transferring, etc., renesas electronics products or technologies, you shall comply with any applicable export control laws and regulations promulgated and administered by the governments of the countries asserting jurisdiction over the parties or transactions. 10. please acknowledge and agree that you shall bear all the losses and damages which are incurred from the misuse or violation of the terms and conditions described in this document, including this notice, and hold renesas electronics harmless, if such misuse or violation results from your resale or making renesas electronics produ cts available any third party. 11. this document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written cons ent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 9251 yonge street, suite 8309 richmond hill, ontario canada l4c 9t3 tel: +1-905-237-2004 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal ii stage, indiranagar, bangalore, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2017 renesas electronics corporation. all rights reserved. colophon 6.0 (rev.3.0-1 november 2016)

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